发明申请
- 专利标题： REDUCED DEFECT SEMICONDUCTOR-ON-INSULATOR HETERO-STRUCTURES
- 专利标题（中）： 减少缺陷半导体绝缘体异质结构
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申请号： US12496006申请日： 2009-07-01
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公开(公告)号： US20110001167A1公开(公告)日： 2011-01-06
- 发明人: Stephen W. Bedell , Jeehwan Kim , Alexander Reznicek , Devendra K. Sadana
- 申请人： Stephen W. Bedell , Jeehwan Kim , Alexander Reznicek , Devendra K. Sadana
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 主分类号： H01L29/267
- IPC分类号： H01L29/267 ; H01L29/165 ; H01L29/161 ; H01L21/20
摘要：
A semiconductor-on-insulator hetero-structure and a method for fabricating the semiconductor-on-insulator hetero-structure include a crystalline substrate and a dielectric layer located thereupon having an aperture that exposes the crystalline substrate. The semiconductor-on-insulator hetero-structure and the method for fabricating the semiconductor-on-insulator hetero-structure also include a semiconductor layer of composition different than the crystalline substrate located within the aperture and upon the dielectric layer. A portion of the semiconductor layer located aligned over the aperture includes a defect. A portion of the semiconductor layer located aligned over the dielectric layer does not include a defect. Upon removing the portion of the semiconductor layer located aligned over the aperture a reduced defect semiconductor-on-insulator hetero-structure is formed.
公开/授权文献
- US08039371B2 Reduced defect semiconductor-on-insulator hetero-structures 公开/授权日：2011-10-18
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