发明申请
US20110006377A1 Patterning Embedded Control Lines for Vertically Stacked Semiconductor Elements
有权
用于垂直堆叠半导体元件的嵌入式控制线图案化
- 专利标题: Patterning Embedded Control Lines for Vertically Stacked Semiconductor Elements
- 专利标题(中): 用于垂直堆叠半导体元件的嵌入式控制线图案化
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申请号: US12502178申请日: 2009-07-13
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公开(公告)号: US20110006377A1公开(公告)日: 2011-01-13
- 发明人: Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
- 申请人: Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
- 申请人地址: US MN Scotts Valley
- 专利权人: SEAGATE TECHNOLOGY LLC
- 当前专利权人: SEAGATE TECHNOLOGY LLC
- 当前专利权人地址: US MN Scotts Valley
- 主分类号: H01L27/105
- IPC分类号: H01L27/105 ; H01L21/18
摘要:
Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
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