发明申请
US20110006377A1 Patterning Embedded Control Lines for Vertically Stacked Semiconductor Elements 有权
用于垂直堆叠半导体元件的嵌入式控制线图案化

Patterning Embedded Control Lines for Vertically Stacked Semiconductor Elements
摘要:
Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
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