公开(公告)号：US20120199915A1

公开(公告)日：2012-08-09

申请号：US13446462

申请日：2012-04-13

申请人： Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

发明人： Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

IPC分类号： H01L27/105

CPC分类号： H01L27/101 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L43/08 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1675

摘要： The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.

摘要翻译： 本发明一般涉及用于垂直堆叠的半导体元件的具有嵌入式（底侧）控制线的装置。 根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。 第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。 所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。 去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

公开(公告)号：US08183126B2

公开(公告)日：2012-05-22

申请号：US12502178

申请日：2009-07-13

申请人： Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

发明人： Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

IPC分类号： H01L21/30

CPC分类号： H01L27/101 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L43/08 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1675

摘要： Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.

摘要翻译： 本发明的各种实施例通常涉及一种用于垂直堆叠的半导体元件的嵌入式（底侧）控制线的设备及其形成方法。 根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。 第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。 所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。 去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

公开(公告)号：US08896070B2

公开(公告)日：2014-11-25

申请号：US13446462

申请日：2012-04-13

申请人： Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

发明人： Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

IPC分类号： H01L45/00 ,  H01L27/24 ,  H01L27/22 ,  H01L43/08 ,  H01L27/10

CPC分类号： H01L27/101 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L43/08 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1675

摘要： The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.

摘要翻译： 本发明一般涉及用于垂直堆叠的半导体元件的具有嵌入式（底侧）控制线的装置。 根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。 第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。 所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。 去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

公开(公告)号：US20110006377A1

公开(公告)日：2011-01-13

申请号：US12502178

申请日：2009-07-13

申请人： Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

发明人： Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

IPC分类号： H01L27/105 ,  H01L21/18

CPC分类号： H01L27/101 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L43/08 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1675

摘要： Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.

摘要翻译： 本发明的各种实施例通常涉及一种用于垂直堆叠的半导体元件的嵌入式（底侧）控制线的设备及其形成方法。 根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。 第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。 所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。 去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

公开(公告)号：US20120080725A1

公开(公告)日：2012-04-05

申请号：US12894405

申请日：2010-09-30

申请人： Peter Nicholas Manos ,  Young Pil Kim ,  Hyung-Kyu Lee ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir ,  Brian Lee ,  Dadi Setiadi

发明人： Peter Nicholas Manos ,  Young Pil Kim ,  Hyung-Kyu Lee ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir ,  Brian Lee ,  Dadi Setiadi

IPC分类号： H01L27/08 ,  H01L21/02

CPC分类号： H01L27/101 ,  G11C11/16 ,  H01L21/823487 ,  H01L27/228 ,  H01L27/2454 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. An electrically conducting interconnect element is deposited onto at least selected vertical pillar transistors and a non-volatile variable resistive memory cell is deposited onto the electrically conducting interconnect layer to form a vertical transistor memory array.

摘要翻译： 一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。 导电互连元件沉积在至少选定的垂直柱晶体管上，并且非挥发性可变电阻存储单元沉积在导电互连层上以形成垂直晶体管存储器阵列。

公开(公告)号：US07965538B2

公开(公告)日：2011-06-21

申请号：US12502224

申请日：2009-07-13

申请人： Yongchul Ahn ,  Antoine Khoueir ,  Shuiyuan Huang ,  Peter Nicholas Manos ,  Maroun Khoury

发明人： Yongchul Ahn ,  Antoine Khoueir ,  Shuiyuan Huang ,  Peter Nicholas Manos ,  Maroun Khoury

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/78 ,  G11C2213/79

摘要： Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal. A formation current is applied through the RRAM cell, and an activation voltage is concurrently applied to the APD to maintain a maximum magnitude of the formation current below a predetermined threshold level.

摘要翻译： 在用于准备用于正常读写操作的单元的RRAM形成过程期间，向电阻随机存取存储器（RRAM）单元提供过电流保护的装置和方法。 根据各种实施例，RRAM单元连接在第一控制线和第二控制线之间，并且主动保护装置（APD）连接在第二控制线和电接地端之间。 通过RRAM单元施加形成电流，并且将激活电压同时施加到APD以将形成电流的最大幅度维持在预定阈值水平以下。

公开(公告)号：US20110007552A1

公开(公告)日：2011-01-13

申请号：US12502224

申请日：2009-07-13

申请人： Yongchul Ahn ,  Antoine Khoueir ,  Shuiyuan Huang ,  Peter Nicholas Manos ,  Maroun Khoury

发明人： Yongchul Ahn ,  Antoine Khoueir ,  Shuiyuan Huang ,  Peter Nicholas Manos ,  Maroun Khoury

IPC分类号： G11C11/00 ,  G11C5/14

CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/78 ,  G11C2213/79

摘要： Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal. A formation current is applied through the RRAM cell, and an activation voltage is concurrently applied to the APD to maintain a maximum magnitude of the formation current below a predetermined threshold level

摘要翻译： 在用于准备用于正常读写操作的单元的RRAM形成过程期间，向电阻随机存取存储器（RRAM）单元提供过电流保护的装置和方法。 根据各种实施例，RRAM单元连接在第一控制线和第二控制线之间，并且主动保护装置（APD）连接在第二控制线和电接地端之间。 通过RRAM单元施加形成电流，并且激活电压同时施加到APD以将形成电流的最大幅度维持在预定阈值水平以下

公开(公告)号：US08193089B2

公开(公告)日：2012-06-05

申请号：US12502220

申请日：2009-07-13

申请人： Antoine Khoueir ,  Yongchul Ahn ,  Peter Nicholas Manos ,  Shuiyan Huang ,  Ivan Petrov Ivanov

发明人： Antoine Khoueir ,  Yongchul Ahn ,  Peter Nicholas Manos ,  Shuiyan Huang ,  Ivan Petrov Ivanov

IPC分类号： H01L21/4763

CPC分类号： H01L21/76846 ,  H01L21/76862

摘要： Various embodiments of the present invention are generally directed to a method of forming a conductive via plug in a semiconductor device. A first and second metal layer are electrically connected by a via plug that is formed by depositing a tungsten seed layer on a plurality of metal barrier layers within a recess using atomic layer deposition. The recess is then filled with tungsten using chemical vapor deposition.

摘要翻译： 本发明的各种实施例通常涉及在半导体器件中形成导电通孔的方法。 通过使用原子层沉积在凹部内的多个金属阻挡层上沉积钨晶种层而形成的通孔塞电连接第一和第二金属层。 然后使用化学气相沉积用凹槽填充钨。

公开(公告)号：US20140071751A1

公开(公告)日：2014-03-13

申请号：US13610433

申请日：2012-09-11

申请人： YoungPil Kim ,  Dadi Setiadi ,  Wei Tian ,  Antoine Khoueir ,  Rodney Virgil Bowman

发明人： YoungPil Kim ,  Dadi Setiadi ,  Wei Tian ,  Antoine Khoueir ,  Rodney Virgil Bowman

IPC分类号： G11C16/16

CPC分类号： G11C16/14 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/16 ,  G11C2013/0073 ,  G11C2211/5646

摘要： Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a soft erasure is performed on a block of memory cells by toggling an erasure status value without otherwise affecting a written state of the cells in the block. The memory cells are subsequently overwritten with a set of data using a write polarity direction determined responsive to the toggled erasure status value.

摘要翻译： 用于管理存储器中的数据的装置和方法，诸如但不限于闪存阵列。 根据一些实施例，通过切换擦除状态值来对存储器单元块执行软擦除，而不影响块中的单元的写入状态。 随后使用响应于切换的擦除状态值确定的写入极性方向用一组数据覆盖存储器单元。

公开(公告)号：US09001578B2

公开(公告)日：2015-04-07

申请号：US13610433

申请日：2012-09-11

申请人： YoungPil Kim ,  Dadi Setiadi ,  Wei Tian ,  Antoine Khoueir ,  Rodney Virgil Bowman

发明人： YoungPil Kim ,  Dadi Setiadi ,  Wei Tian ,  Antoine Khoueir ,  Rodney Virgil Bowman

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/16 ,  G11C11/56 ,  G11C16/14

CPC分类号： G11C16/14 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/16 ,  G11C2013/0073 ,  G11C2211/5646

摘要： Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a soft erasure is performed on a block of memory cells by toggling an erasure status value without otherwise affecting a written state of the cells in the block. The memory cells are subsequently overwritten with a set of data using a write polarity direction determined responsive to the toggled erasure status value.

摘要翻译： 用于管理存储器中的数据的装置和方法，诸如但不限于闪存阵列。 根据一些实施例，通过切换擦除状态值来对存储器单元块执行软擦除，而不影响块中的单元的写入状态。 随后使用响应于切换的擦除状态值确定的写入极性方向用一组数据覆盖存储器单元。