Magnetic shield layout (10, 10 A-10 G) arranged for an integrated circuit of a semiconductor device comprising at least a first inductor (1) having a first crosssectional inductor-area (11), and at least a second inductor (2) having a second crosssectional inductor-area (12), wherein the inductor-areas (11, 12) are located in an inductor-plane (P) and wherein the first and second inductors (1, 2) in operation are subject to an induction coupling; at least one magnetic shield (20) for reducing the induction coupling, said magnetic shield having a conductive path (21) marking a first crosssectional shield-area (13) assigned to the first cross-sectional inductor-area (11) and a second crosssectional shield-area (14) assigned to the second crosssectional inductor-area (12); wherein the shield-areas (13, 14) are conductively and continuously connected by the conductive path (21) such that in operation a magnetic field generated by the first inductor (1) is largely cancelled by the magnetic field of the second cross-sectional shield-area (12) and/or a magnetic field generated by the second inductor (2) is largely cancelled by the magnetic field of the first cross-sectional shield-area (11).