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    INDUCTOR
    1.
    发明申请
    INDUCTOR 有权
    电感器

    公开(公告)号：US20110148558A1

    公开(公告)日：2011-06-23

    申请号：US12973848

    申请日：2010-12-20

    Applicant: Alexè Levan Nazarian ,  Lukas Frederik TIEMEIJER

    Inventor： Alexè Levan Nazarian ,  Lukas Frederik TIEMEIJER

    IPC: H01F27/28

    CPC classification number: H01F17/0006 ,  H01F5/003 ,  H01F21/12 ,  H01F27/2804 ,  H01F27/34 ,  H01F2017/0073

    Abstract: An inductor includes a conductive track forming at least three inductor turns. The conductive track has a plurality of track sections. The inductor also includes at least two groups of crossing points, each crossing point comprising a location at which the conductive track crosses over itself. The crossing points of each group collectively reverse the order of at least some of the track sections in the inductor, such that inner track sections of the conductive track cross over to become respective outer track sections, and such that outer track sections of the conductive track cross over to become respective inner track sections.

    Abstract translation: 电感器包括形成至少三个电感线圈的导电轨迹。 导电轨道具有多个轨道部分。 电感器还包括至少两组交叉点，每个交叉点包括导电轨道自身跨越的位置。 每个组的交叉点共同地反转电感器中的至少一些轨道部分的顺序，使得导电轨道的内部轨道部分交叉成为相应的外部轨道部分，并且使得导电轨道的外部轨道部分 交叉成为相应的内轨道部分。

    High frequency transistor layout for low source drain capacitance
    2.
    发明授权
    High frequency transistor layout for low source drain capacitance 有权
    用于低源极漏极电容的高频晶体管布局

    公开(公告)号：US07928517B2

    公开(公告)日：2011-04-19

    申请号：US11630855

    申请日：2005-06-22

    Applicant: Lukas Frederik Tiemeijer

    Inventor： Lukas Frederik Tiemeijer

    IPC: H01L27/088

    CPC classification number: H01L29/41758 ,  H01L23/4824 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An RF field effect transistor has a gate electrode, and comb shaped drain and source electrodes, fingers of the comb shaped drain being arranged to be interleaved with fingers of the source electrode, the source and drain electrodes having multiple layers (110,120,130,140). An amount of the interleaving is different in each layer, to enable optimization, particularly for low parasitic capacitance without losing all the advantage of low current density provided by the multiple layers. The interleaving is reduced for layers further from the gate electrode by having shorter fingers. The reduction in interleaving can be optimized for minimum capacitance, by a steeper reduction in interleaving, or for minimum lateral current densities in source and drain fingers, by a more gradual reduction in interleaving. This can enable operation at higher temperatures or at higher input bias currents, while still meeting the requirements of electro-migration rules.

    Abstract translation: RF场效应晶体管具有栅电极，梳形漏极和源电极，梳状漏极的指状物被布置成与源电极的指状物交错，源极和漏极具有多个层（110,120,130,140）。 交织的量在每层中是不同的，以便能够优化，特别是对于低寄生电容，而不会失去由多层提供的低电流密度的所有优点。 通过具有较短的手指，与栅极电极进一步层的交织减少。 通过交织的逐渐减少，交织的减少可以针对最小电容，交叉的更陡的减少或源极和漏极的最小横向电流密度进行优化。 这可以在更高的温度或更高的输入偏置电流下工作，同时仍然满足电迁移规则的要求。

    Method for calibrating and de-embedding, set of devices for de-embedding and vector network analyzer
    3.
    发明授权
    Method for calibrating and de-embedding, set of devices for de-embedding and vector network analyzer 失效
    校准和解嵌方法，去嵌入设备和矢量网络分析仪

    公开(公告)号：US07026829B2

    公开(公告)日：2006-04-11

    申请号：US10514327

    申请日：2003-05-08

    Applicant: Lukas Frederik Tiemeijer

    Inventor： Lukas Frederik Tiemeijer

    IPC: G01R27/04 ,  G01R35/00 ,  G01D18/00

    CPC classification number: G01R27/28 ,  G01R35/005

    Abstract: The accuracy of a method for calibrating an N terminal microwave measurement network (10), the method comprising the measurement of network parameter values of a load device (43), depends on the knowledge of the parasitic impedance of the load device (43). According to the invention, the accuracy of the method is improved by at least approximately determining the parasitic impedances of the load device (43). In one embodiment this is achieved by measuring network parameter values of an auxiliary open device (44), having a substantially identical parasitic impedance as the load device (43). The accuracy is further increased by measuring network parameter values of an auxiliary short device (45), having a substantially identical parasitic impedance as the load device (43). A similar principle can be used for de-embedding a device under test. A load device (43), an auxiliary open device (44) and an auxiliary short device (45) having substantially identical parasitic impedances are disclosed.

    Abstract translation: 用于校准N端微波测量网络（10）的方法的准确性，包括对负载设备（43）的网络参数值的测量的方法取决于负载设备（43）的寄生阻抗的知识。 根据本发明，通过至少近似地确定负载装置（43）的寄生阻抗来提高该方法的精度。 在一个实施例中，这通过测量具有与负载装置（43）基本上相同的寄生阻抗的辅助开路装置（44）的网络参数值来实现。 通过测量与负载装置（43）具有基本上相同的寄生阻抗的辅助短路装置（45）的网络参数值来进一步提高精度。 类似的原理可以用于解嵌入被测设备。 公开了具有基本上相同的寄生阻抗的负载装置（43），辅助开启装置（44）和辅助短路装置（45）。

    Fringe capacitor circuit
    4.
    发明授权
    Fringe capacitor circuit 有权
    边缘电容电路

    公开(公告)号：US08594604B2

    公开(公告)日：2013-11-26

    申请号：US12641858

    申请日：2009-12-18

    Applicant: Edwin van der Heijden ,  Lukas Frederik Tiemeijer ,  Maristella Spella

    Inventor： Edwin van der Heijden ,  Lukas Frederik Tiemeijer ,  Maristella Spella

    IPC: H04B1/10

    CPC classification number: H01L23/5223 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: Capacitive circuits are implemented with desirable quality factors in various implementations. According to an example embodiment, a fringe capacitor includes two capacitive circuits (e.g., plates), respectively having a plurality of capacitive fingers extending from an end structure, and respectively having a connecting pin that is adjacent the connecting pin of the other capacitive circuit, on a common side fringe capacitor. The capacitive fingers are arranged in stacked layers, with vias connecting the fingers in different layers back to the connecting pins.

    Abstract translation: 电容电路在各种实现中以期望的质量因子实现。 根据示例性实施例，边缘电容器包括分别具有从端部结构延伸的多个电容指状物并且分别具有与另一个电容电路的连接引脚相邻的连接引脚的两个电容电路（例如，板） 在共同的边缘电容器上。 电容指状物被布置成堆叠层，通孔将不同层中的指状物连接回连接销。

    Fringe Capacitor Circuit
    5.
    发明申请
    Fringe Capacitor Circuit 有权
    边缘电容电路

    公开(公告)号：US20110151803A1

    公开(公告)日：2011-06-23

    申请号：US12641858

    申请日：2009-12-18

    Applicant: Edwin van der Heijden ,  Lukas Frederik Tiemeijer ,  Maristella Spella

    Inventor： Edwin van der Heijden ,  Lukas Frederik Tiemeijer ,  Maristella Spella

    IPC: H04B1/38 ,  H01G4/30

    CPC classification number: H01L23/5223 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: Capacitive circuits are implemented with desirable quality factors in various implementations. According to an example embodiment, a fringe capacitor includes two capacitive circuits (e.g., plates), respectively having a plurality of capacitive fingers extending from an end structure, and respectively having a connecting pin that is adjacent the connecting pin of the other capacitive circuit, on a common side fringe capacitor. The capacitive fingers are arranged in stacked layers, with vias connecting the fingers in different layers back to the connecting pins.

    Abstract translation: 电容电路在各种实现中以期望的质量因子实现。 根据示例性实施例，边缘电容器包括分别具有从端部结构延伸的多个电容指状物并且分别具有与另一个电容电路的连接引脚相邻的连接引脚的两个电容电路（例如，板） 在共同的边缘电容器上。 电容指状物被布置成堆叠层，通孔将不同层中的指状物连接回连接销。

    PLANAR, MONOLITHICALLY INTEGRATED COIL
    6.
    发明申请
    PLANAR, MONOLITHICALLY INTEGRATED COIL 有权
    平面，单层集成线圈

    公开(公告)号：US20110128111A1

    公开(公告)日：2011-06-02

    申请号：US13002152

    申请日：2009-06-30

    Applicant: Freddy Roozeboom ,  Derk Reefman ,  Johan Hendrik Klootwijk ,  Lukas Frederik Tiemeijer ,  Jaap Ruigrok

    Inventor： Freddy Roozeboom ,  Derk Reefman ,  Johan Hendrik Klootwijk ,  Lukas Frederik Tiemeijer ,  Jaap Ruigrok

    IPC: H01F27/36 ,  H01F5/00

    CPC classification number: H01F17/0006 ,  H01F27/365 ,  H01F2017/0066 ,  H01F2017/008

    Abstract: The present invention provides a means to integrate planar coils on silicon, while providing a high inductance. This high inductance is achieved through a special back- and front sided shielding of a material. In many applications, high-value inductors are a necessity. In particular, this holds for applications in power management. In these applications, the inductors are at least 5 of the order of 1 μH, and must have an equivalent series resistance of less than 0.1 Ω. For this reason, those inductors are always bulky components, of a typical size of 2×2×1 mm 3, which make a fully integrated solution impossible. On the other hand, integrated inductors, which can monolithically be integrated, do exist. However, these inductors suffer either from low inductance values, or 10 very-high DC resistance values.

    Abstract translation: 本发明提供了一种在硅上集成平面线圈同时提供高电感的方法。 这种高电感通过材料的特殊背面和前面屏蔽来实现。 在许多应用中，高值感应器是必需的。 特别是适用于电源管理的应用。 在这些应用中，电感器的电阻值至少为1μH，必须具有小于0.1Ω的等效串联电阻。 因此，这些电感器通常是典型尺寸为2×2×1mm 3的体积较大的部件，这使得完全集成的解决方案不可能。 另一方面，确实存在可以整体集成的集成电感器。 然而，这些电感器受到低电感值或10个非常高的直流电阻值的影响。

    MAGNETIC SHIELD LAYOUT, SEMICONDUCTOR DEVICE AND APPLICATION
    7.
    发明申请
    MAGNETIC SHIELD LAYOUT, SEMICONDUCTOR DEVICE AND APPLICATION 审中-公开
    磁屏蔽布局，半导体器件及应用

    公开(公告)号：US20110006872A1

    公开(公告)日：2011-01-13

    申请号：US12831593

    申请日：2010-07-07

    Applicant: Alexe Levan Nazarian ,  Lukas Frederik Tiemeijer

    Inventor： Alexe Levan Nazarian ,  Lukas Frederik Tiemeijer

    IPC: H01F27/36

    CPC classification number: H01F17/0006 ,  H01F27/289 ,  H01F27/367 ,  H01F2017/0073 ,  H01F2017/008 ,  H01Q1/525 ,  H01Q7/00 ,  H03B5/1296

    Abstract: Magnetic shield layout (10, 10 A-10 G) arranged for an integrated circuit of a semiconductor device comprising at least a first inductor (1) having a first crosssectional inductor-area (11), and at least a second inductor (2) having a second crosssectional inductor-area (12), wherein the inductor-areas (11, 12) are located in an inductor-plane (P) and wherein the first and second inductors (1, 2) in operation are subject to an induction coupling; at least one magnetic shield (20) for reducing the induction coupling, said magnetic shield having a conductive path (21) marking a first crosssectional shield-area (13) assigned to the first cross-sectional inductor-area (11) and a second crosssectional shield-area (14) assigned to the second crosssectional inductor-area (12); wherein the shield-areas (13, 14) are conductively and continuously connected by the conductive path (21) such that in operation a magnetic field generated by the first inductor (1) is largely cancelled by the magnetic field of the second cross-sectional shield-area (12) and/or a magnetic field generated by the second inductor (2) is largely cancelled by the magnetic field of the first cross-sectional shield-area (11).

    Abstract translation: 布置成用于半导体器件的集成电路的磁屏蔽布局（10,10A-10G）包括至少第一电感器（1），其具有第一横截面电感器区域（11）和至少第二电感器（2） 具有第二横截面电感器区域（12），其中电感器区域（11,12）位于电感器平面（P）中，并且其中操作中的第一和第二电感器（1,2）经受感应 耦合; 至少一个用于减小感应耦合的磁屏蔽（20），所述磁屏蔽具有标记分配给第一截面电感器区域（11）的第一横截面屏蔽区域（13）的导电路径（21） 分配给第二横截面电感器区域（12）的横截面屏蔽区域（14）; 其中所述屏蔽区域（13,14）由所述导电路径（21）导电连续地连接，使得在操作中由所述第一电感器（1）产生的磁场被所述第二横截面的磁场大大抵消 屏蔽区域（12）和/或由第二电感器（2）产生的磁场被第一横截面屏蔽区域（11）的磁场大大抵消。

    Planar inductor
    8.
    发明授权
    Planar inductor 有权
    平面电感

    公开(公告)号：US08217747B2

    公开(公告)日：2012-07-10

    申请号：US11630586

    申请日：2005-06-17

    Applicant: Lukas Frederik Tiemeijer

    Inventor： Lukas Frederik Tiemeijer

    IPC: H01F5/00 ,  H01F21/12 ,  H01F27/29 ,  H01F27/28

    CPC classification number: H01F21/12 ,  H01F17/0006 ,  H01F2017/0046 ,  H01F2017/0053 ,  H01F2021/125

    Abstract: A planar inductor (50) comprises a conductive path in the form of a spiral pattern (53A-53D, 54A-54D). A conductive connecting path (62A, 63) connects a terminal (60) to an intermediate tap point (61A). The connecting path comprises at least one path portion which is radially directed with respect to the spiral pattern (53A-53D). The connecting path (62A, 63) can be routed via the inside of the spiral pattern. Where the connecting path comprises only radially-directed path portions, they are commonly joined at the center (64) of the spiral pattern. Multiple path portions (62A, 62B) can each connect to the intermediate tap point of a respective conductive path. The connecting path can use a further conductive track (85) which is parallel to the conductive path which forms the spiral pattern.

    Abstract translation: 平面电感器（50）包括呈螺旋图案形式的导电路径（53A-53D，54A-54D）。 导电连接路径（62A，63）将端子（60）连接到中间抽头点（61A）。 连接路径包括相对于螺旋图案（53A-53D）径向定向的至少一个路径部分。 连接路径（62A，63）可以经由螺旋图案的内部布线。 在连接路径仅包括径向路径部分的情况下，它们通常在螺旋图案的中心（64）处连接。 多个路径部分（62A，62B）可以各自连接到相应导电路径的中间抽头点。 连接路径可以使用与形成螺旋图案的导电路径平行的另外的导电轨道（85）。

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