A signal processing circuit comprises a frequency up-conversion circuit (14, 60) for performing up-conversion with a first local oscillator frequency and a frequency down-conversion circuit (16) for performing down-conversion with a second local oscillator frequency. A digital signal processor (10) controls supply first signals representing a first complex signal to the up-conversion circuit, and receives second signals representing a second complex signal. The digital signal processor controls a compensation of I/Q mismatch of results of up-conversion and/or down-conversion. The digital signal processor (10) switches to a calibration mode for selecting a parameter of said compensation. In the calibration mode the first and second local oscillator frequencies have a frequency offset with respect to each other. The digital signal processor (10) measures an amplitude of a frequency component at a frequency corresponding to mismatch in one and not more than one of the results of up-conversion and/or down-conversion, and selects the parameter dependent on the amplitude.