公开(公告)号：US08532224B2

公开(公告)日：2013-09-10

申请号：US12735201

申请日：2008-12-19

Applicant: Remco Van De Beek ,  Domine Leenaerts ,  Charles Razzell ,  Jozef R. M. Ervoet

Inventor： Remco Van De Beek ,  Domine Leenaerts ,  Charles Razzell ,  Jozef R. M. Ervoet

IPC: H03C3/00

CPC classification number: H03D7/00 ,  H03D2200/0047 ,  H03D2200/0082 ,  H04L5/0007 ,  H04L27/0014 ,  H04L27/227 ,  H04L27/2601 ,  H04L27/364 ,  H04L2027/0016 ,  H04L2027/0022 ,  H04L2027/0032 ,  H04L2027/0065

Abstract: A signal processing circuit comprises a frequency up-conversion circuit (14, 60) for performing up-conversion with a first local oscillator frequency and a frequency down-conversion circuit (16) for performing down-conversion with a second local oscillator frequency. A digital signal processor (10) controls supply first signals representing a first complex signal to the up-conversion circuit, and receives second signals representing a second complex signal. The digital signal processor controls a compensation of I/Q mismatch of results of up-conversion and/or down-conversion. The digital signal processor (10) switches to a calibration mode for selecting a parameter of said compensation. In the calibration mode the first and second local oscillator frequencies have a frequency offset with respect to each other. The digital signal processor (10) measures an amplitude of a frequency component at a frequency corresponding to mismatch in one and not more than one of the results of up-conversion and/or down-conversion, and selects the parameter dependent on the amplitude.

Abstract translation: 信号处理电路包括用于以第一本地振荡器频率执行上变频的升频转换电路（14,60）和用于执行具有第二本机振荡器频率的下变频的降频转换电路（16）。 数字信号处理器（10）控制向上转换电路提供表示第一复信号的第一信号，并接收表示第二复信号的第二信号。 数字信号处理器控制上转换和/或下转换结果的I / Q不匹配的补偿。 数字信号处理器（10）切换到用于选择所述补偿的参数的校准模式。 在校准模式中，第一和第二本地振荡器频率相对于彼此具有频率偏移。 数字信号处理器（10）以对应于上变频和/或下变频结果中的一个且不超过一个失配的频率测量频率分量的幅度，并且根据幅度选择参数。

公开(公告)号：US20110019773A1

公开(公告)日：2011-01-27

申请号：US12735201

申请日：2008-12-19

Applicant: Remco Van De Beek ,  Domine Leenaerts ,  Charles Razzell ,  Jozef R. Ervoet

Inventor： Remco Van De Beek ,  Domine Leenaerts ,  Charles Razzell ,  Jozef R. Ervoet

IPC: H04L27/06

CPC classification number: H03D7/00 ,  H03D2200/0047 ,  H03D2200/0082 ,  H04L5/0007 ,  H04L27/0014 ,  H04L27/227 ,  H04L27/2601 ,  H04L27/364 ,  H04L2027/0016 ,  H04L2027/0022 ,  H04L2027/0032 ,  H04L2027/0065

Abstract: A signal processing circuit comprises a frequency up-conversion circuit (14, 60) for performing up-conversion with a first local oscillator frequency and a frequency down-conversion circuit (16) for performing down-conversion with a second local oscillator frequency. A digital signal processor (10) controls supply first signals representing a first complex signal to the up-conversion circuit, and receives second signals representing a second complex signal. The digital signal processor controls a compensation of I/Q mismatch of results of up-conversion and/or down-conversion. The digital signal processor (10) switches to a calibration mode for selecting a parameter of said compensation. In the calibration mode the first and second local oscillator frequencies have a frequency offset with respect to each other. The digital signal processor (10) measures an amplitude of a frequency component at a frequency corresponding to mismatch in one and not more than one of the results of up-conversion and/or down-conversion, and selects the parameter dependent on the amplitude.

Abstract translation: 信号处理电路包括用于以第一本地振荡器频率执行上变频的升频转换电路（14,60）和用于执行具有第二本机振荡器频率的下变频的降频转换电路（16）。 数字信号处理器（10）控制向上转换电路提供表示第一复信号的第一信号，并接收表示第二复信号的第二信号。 数字信号处理器控制上转换和/或下转换结果的I / Q不匹配的补偿。 数字信号处理器（10）切换到用于选择所述补偿的参数的校准模式。 在校准模式中，第一和第二本地振荡器频率相对于彼此具有频率偏移。 数字信号处理器（10）以对应于上变频和/或下变频结果中的一个且不超过一个失配的频率测量频率分量的幅度，并且根据幅度选择参数。