Invention Application
US20110043251A1 Opportunistic Timing Control in Mixed-Signal System-On-Chip Designs
有权
混合信号系统芯片设计中的机会时序控制
- Patent Title: Opportunistic Timing Control in Mixed-Signal System-On-Chip Designs
- Patent Title (中): 混合信号系统芯片设计中的机会时序控制
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Application No.: US12630999Application Date: 2009-12-04
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Publication No.: US20110043251A1Publication Date: 2011-02-24
- Inventor: Yoshinori Kusuda , Michael Coln , Gary Carreau
- Applicant: Yoshinori Kusuda , Michael Coln , Gary Carreau
- Main IPC: H03K19/00
- IPC: H03K19/00

Abstract:
An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive.
Public/Granted literature
- US08203357B2 Opportunistic timing control in mixed-signal system-on-chip designs Public/Granted day:2012-06-19
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