发明申请
- 专利标题: METHOD OF MANUFACTURING LAYER-STACKED WIRING
- 专利标题(中): 制造层叠布线的方法
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申请号: US12942381申请日: 2010-11-09
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公开(公告)号: US20110053354A1公开(公告)日: 2011-03-03
- 发明人: Jun TANAKA , Hiroshi KANOH
- 申请人: Jun TANAKA , Hiroshi KANOH
- 申请人地址: JP Tokyo
- 专利权人: NEC CORPORATION
- 当前专利权人: NEC CORPORATION
- 当前专利权人地址: JP Tokyo
- 优先权: JP2006-078653 20060322
- 主分类号: H01L21/324
- IPC分类号: H01L21/324 ; H01L21/20
摘要:
A layer-stacked wiring made up of a microcrystalline silicon thin film and a metal thin film is provided which is capable of suppressing an excessive silicide formation reaction between the microcrystalline silicon thin film and metal thin film, thereby preventing peeling of the thin film. In a polycrystalline silicon TFT (Thin Film Transistor) using the layer-stacked wiring, the microcrystalline silicon thin film is so configured that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of the microcrystalline silicon thin film amount to 15% or less of total number of crystal grains or that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of the microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains making up the microcrystalline silicon thin film.
公开/授权文献
- US08026162B2 Method of manufacturing layer-stacked wiring 公开/授权日:2011-09-27
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