发明申请
US20110070697A1 METHOD FOR FABRICATING STACK STRUCTURE OF SEMICONDUCTOR PACKAGES
有权
用于制作半导体封装的堆叠结构的方法
- 专利标题: METHOD FOR FABRICATING STACK STRUCTURE OF SEMICONDUCTOR PACKAGES
- 专利标题(中): 用于制作半导体封装的堆叠结构的方法
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申请号: US12955256申请日: 2010-11-29
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公开(公告)号: US20110070697A1公开(公告)日: 2011-03-24
- 发明人: Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
- 申请人: Fang-Lin Tsai , Ho-Yi Tsai , Han-Ping Pu , Cheng-Hsu Hsiao
- 申请人地址: TW Taichung
- 专利权人: SILICONWARE PRECISION INDUSTRIES CO., LTD.
- 当前专利权人: SILICONWARE PRECISION INDUSTRIES CO., LTD.
- 当前专利权人地址: TW Taichung
- 优先权: TW095114501 20060424
- 主分类号: H01L21/48
- IPC分类号: H01L21/48
摘要:
A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.
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