发明申请
US20110122702A1 PROGRAMMING MEMORY WITH SENSING-BASED BIT LINE COMPENSATION TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING 有权
具有基于感测的位线补偿的编程存储器可减少通道至浮动门的耦合

  • 专利标题: PROGRAMMING MEMORY WITH SENSING-BASED BIT LINE COMPENSATION TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING
  • 专利标题(中): 具有基于感测的位线补偿的编程存储器可减少通道至浮动门的耦合
  • 申请号: US12624595
    申请日: 2009-11-24
  • 公开(公告)号: US20110122702A1
    公开(公告)日: 2011-05-26
  • 发明人: Yan Li
  • 申请人: Yan Li
  • 主分类号: G11C16/10
  • IPC分类号: G11C16/10 G11C16/04 G11C16/26
PROGRAMMING MEMORY WITH SENSING-BASED BIT LINE COMPENSATION TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING
摘要:
During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. In connection with a programming iteration, unselected bit lines voltages are stepped up to induce coupling to selected bit lines, and the amount of coupling which is experienced by the selected bit lines is sensed. When a program pulse is applied, voltages of the selected bit lines are set based on the amount of coupling. The bit line voltage is set higher when more coupling is sensed. The amount of coupling experience by a given selected bit line is a function of its proximity to unselected bit lines. One or more coupling thresholds can be used to indicate that a given selected bit line has one or two adjacent unselected bit lines, respectively.
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