发明申请
US20110134703A1 Nonvolatile Memory and Method With Reduced Program Verify by Ignoring Fastest And/Or Slowest Programming Bits 有权
通过忽略最快和/或最慢的编程位,减少程序验证的非易失性存储器和方法

  • 专利标题: Nonvolatile Memory and Method With Reduced Program Verify by Ignoring Fastest And/Or Slowest Programming Bits
  • 专利标题(中): 通过忽略最快和/或最慢的编程位,减少程序验证的非易失性存储器和方法
  • 申请号: US13029848
    申请日: 2011-02-17
  • 公开(公告)号: US20110134703A1
    公开(公告)日: 2011-06-09
  • 发明人: Yan LiYupin Kawing FongSitu Lung Chan
  • 申请人: Yan LiYupin Kawing FongSitu Lung Chan
  • 主分类号: G11C16/10
  • IPC分类号: G11C16/10
Nonvolatile Memory and Method With Reduced Program Verify by Ignoring Fastest And/Or Slowest Programming Bits
摘要:
A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.
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