发明申请
US20110164675A1 DIGITAL PLL CIRCUIT AND COMMUNICATION DEVICE 有权
数字PLL电路和通信设备

DIGITAL PLL CIRCUIT AND COMMUNICATION DEVICE
摘要:
In a digital PLL circuit outputting a clock signal with a frequency obtained by multiplying a frequency of a reference signal by a frequency command word (a frequency ratio), an RPA serially adds a frequency command word containing a fractional component. An output of the RPA is input to a minute phase error generator. The phase error generator generates a plurality of threshold values close to an actual amplitude value of the reference signal based on the fractional portion of the serially added value of the frequency command word, calculates the amplitude value of the reference signal and a phase error of the reference signal corresponding to the amplitude value based on the threshold values, and calculates a minute phase error between the reference signal and the output clock.
公开/授权文献
信息查询
0/0