发明申请
- 专利标题: DIGITAL PLL CIRCUIT AND COMMUNICATION DEVICE
- 专利标题(中): 数字PLL电路和通信设备
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申请号: US13049645申请日: 2011-03-16
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公开(公告)号: US20110164675A1公开(公告)日: 2011-07-07
- 发明人: Fumiaki SENOUE , Kouji Okamoto
- 申请人: Fumiaki SENOUE , Kouji Okamoto
- 申请人地址: JP Osaka
- 专利权人: PANASONIC CORPORATION
- 当前专利权人: PANASONIC CORPORATION
- 当前专利权人地址: JP Osaka
- 优先权: JP2008-273476 20081023
- 主分类号: H04N7/12
- IPC分类号: H04N7/12 ; H03L7/085
摘要:
In a digital PLL circuit outputting a clock signal with a frequency obtained by multiplying a frequency of a reference signal by a frequency command word (a frequency ratio), an RPA serially adds a frequency command word containing a fractional component. An output of the RPA is input to a minute phase error generator. The phase error generator generates a plurality of threshold values close to an actual amplitude value of the reference signal based on the fractional portion of the serially added value of the frequency command word, calculates the amplitude value of the reference signal and a phase error of the reference signal corresponding to the amplitude value based on the threshold values, and calculates a minute phase error between the reference signal and the output clock.
公开/授权文献
- US08780974B2 Digital PLL circuit and communication device 公开/授权日:2014-07-15
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