发明申请
- 专利标题: Timing Point Selection For A Static Timing Analysis In The Presence Of Interconnect Electrical Elements
- 专利标题(中): 在互连电气元件存在下的静态时序分析的时序点选择
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申请号: US12652338申请日: 2010-01-05
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公开(公告)号: US20110167395A1公开(公告)日: 2011-07-07
- 发明人: Jeffrey P. Soreff , Barry Lee Dorfman , Jeffrey G. Hemmett , Ravichander Ledalla , Vasant Rao , Fred Lei Yang
- 申请人: Jeffrey P. Soreff , Barry Lee Dorfman , Jeffrey G. Hemmett , Ravichander Ledalla , Vasant Rao , Fred Lei Yang
- 申请人地址: US NY ARMONK
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY ARMONK
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point. It further also applies to interconnect with other two-port parasitic elements, to cases where only a subset of receiver pins on the net require accurate timing, and to cases where a set of electrical nodes, rather than a single node, partition all paths from drivers to receivers on a net.
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