公开(公告)号：US08201120B2

公开(公告)日：2012-06-12

申请号：US12652338

申请日：2010-01-05

申请人： Jeffrey P. Soreff ,  Barry Lee Dorfman ,  Jeffrey G. Hemmett ,  Ravichander Ledalla ,  Vasant Rao ,  Fred Lei Yang

发明人： Jeffrey P. Soreff ,  Barry Lee Dorfman ,  Jeffrey G. Hemmett ,  Ravichander Ledalla ,  Vasant Rao ,  Fred Lei Yang

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5031

摘要： A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point. It further also applies to interconnect with other two-port parasitic elements, to cases where only a subset of receiver pins on the net require accurate timing, and to cases where a set of electrical nodes, rather than a single node, partition all paths from drivers to receivers on a net.

摘要翻译： 一种用于选择电气互连网络中用于静态时序分析的电气仿真中的定时点的方法和系统，以提高精度。 本发明的方法包括发现在互连的电气模型中的阻塞点，所述互连的所有路径对于所述路由器必须在某些类型的网络上通过。 然后，该方法使用其存在的阻塞点电子节点作为驱动网络的逻辑门的输出定时点。 该方法解决了由于同一互连网上的不同驱动器引脚之间的电阻引起的不准确性的问题，尽管它也可以应用于解决由于与相同接收器定时点相关联的不同接收器引脚之间的电阻引起的类似不准确性。 它还适用于与其他双端口寄生元件的互连，仅在网络上的接收器引脚的子集需要精确的定时的情况下，以及一组电气节点而不是单个节点将所有路径从 驱动程序到网络上的接收器。

公开(公告)号：US20110167395A1

公开(公告)日：2011-07-07

申请号：US12652338

申请日：2010-01-05

申请人： Jeffrey P. Soreff ,  Barry Lee Dorfman ,  Jeffrey G. Hemmett ,  Ravichander Ledalla ,  Vasant Rao ,  Fred Lei Yang

发明人： Jeffrey P. Soreff ,  Barry Lee Dorfman ,  Jeffrey G. Hemmett ,  Ravichander Ledalla ,  Vasant Rao ,  Fred Lei Yang

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point. It further also applies to interconnect with other two-port parasitic elements, to cases where only a subset of receiver pins on the net require accurate timing, and to cases where a set of electrical nodes, rather than a single node, partition all paths from drivers to receivers on a net.

摘要翻译： 一种用于选择电气互连网络中用于静态时序分析的电气仿真中的定时点的方法和系统，以提高精度。 本发明的方法包括发现在互连的电气模型中的阻塞点，所述互连的所有路径对于所述路由器必须在某些类型的网络上通过。 然后，该方法使用其存在的阻塞点电子节点作为驱动网络的逻辑门的输出定时点。 该方法解决了由于同一互连网上的不同驱动器引脚之间的电阻引起的不准确性的问题，尽管它也可以用于解决由于与相同接收器定时点相关联的不同接收器引脚之间的电阻引起的类似不准确性。 它还适用于与其他双端口寄生元件的互连，仅在网络上的接收器引脚的子集需要精确的定时的情况下，以及一组电气节点而不是单个节点将所有路径从 驱动程序到网络上的接收器。