A circuit (10) includes a circuit input (12), a circuit output (16) and a one or more delay elements (22) positioned between the circuit input (12) and the circuit output (16). The delay elements (22) each include a differential input pair (234), a latch stage (236) and a delay controller (244A1, 244A2, 244B1, 244B2). The delay controller (244A1, 244A2, 244B1, 244B2) selectively apportions current between the differential input pair (234) and the latch stage (236) to achieve a desired delay value for the circuit (10). The circuit (10) can also include a feedback loop (18) that calibrates a DC offset of the delay elements (22). The delay elements (22) can include two or more sets of resistive loads (238A, 238B) and a rate controller (241). The rate controller (241) controls an on/off state of the resistive loads (238A, 238B) to selectively switch between full resistance and half resistance. The rate controller (241) can also control the level of current (I1, I2) received by the differential input pair (234) and the latch stage (236) to control the delay value.