发明申请
US20110182125A1 SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF DATA ERASE IN THE SEMICONDUCTOR MEMORY DEVICE
审中-公开
半导体存储器件，半导体器件和半导体存储器件中的数据擦除方法
- 专利标题： SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF DATA ERASE IN THE SEMICONDUCTOR MEMORY DEVICE
- 专利标题（中）： 半导体存储器件，半导体器件和半导体存储器件中的数据擦除方法
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申请号： US12883474申请日： 2010-09-16
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公开(公告)号： US20110182125A1公开(公告)日： 2011-07-28
- 发明人: Mikihiko ITOH , Takeshi Nakano , Michio Nakagawa
- 申请人： Mikihiko ITOH , Takeshi Nakano , Michio Nakagawa
- 申请人地址： JP Tokyo
- 专利权人： KABUSHIKI KAISHA TOSHIBA
- 当前专利权人： KABUSHIKI KAISHA TOSHIBA
- 当前专利权人地址： JP Tokyo
- 优先权： JP2010-015731 20100127
- 主分类号： G11C16/16
- IPC分类号： G11C16/16
摘要：
A semiconductor memory device in accordance with an embodiment comprises a memory cell array and an erase voltage generating circuit. The memory cell array is configured as an arrangement of nonvolatile memory cells. The erase voltage generating circuit is configured to generate an erase voltage for performing data erase of the memory cell array. The erase voltage generating circuit is configured to set, in a data erase mode where the erase voltage is applied to a selected region of the memory cell array in a plurality of erase cycles, a rise waveform of the erase voltage in an initial stage of the plurality of erase cycles to be less steep than a rise waveform of the erase voltage in subsequent cycles.
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