发明申请
US20110227171A1 HIGH-K DIELECTRIC AND METAL GATE STACK WITH MINIMAL OVERLAP WITH ISOLATION REGION 有权
具有隔离区域的最小重叠的高K电介质和金属栅极堆叠

HIGH-K DIELECTRIC AND METAL GATE STACK WITH MINIMAL OVERLAP WITH ISOLATION REGION
摘要:
A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.
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