发明申请
US20110227232A1 CRENULATED WIRING STRUCTURE AND METHOD FOR INTEGRATED CIRCUIT INTERCONNECTS 失效
用于集成电路互连的成形接线结构和方法

CRENULATED WIRING STRUCTURE AND METHOD FOR INTEGRATED CIRCUIT INTERCONNECTS
摘要:
A method for forming crenulated conductors and a device having crenulated conductors includes forming a hardmask layer on a dielectric layer, and patterning the hardmask layer. Trenches are etched in the dielectric layer using the hardmask layer such that the trenches have shallower portions and deeper portions alternating along a length of the trench. A conductor is deposited in the trenches such that crenulated conductive lines are formed having different depths periodically disposed along the length of the conductive line.
信息查询
0/0