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1.发明申请公开(公告)号：US20110227232A1
公开(公告)日：2011-09-22
申请号：US12724903
申请日：2010-03-16
IPC分类号： H01L23/528 , H01L21/768
CPC分类号： H01L23/5283 , H01L21/31144 , H01L21/76804 , H01L21/76816 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method for forming crenulated conductors and a device having crenulated conductors includes forming a hardmask layer on a dielectric layer, and patterning the hardmask layer. Trenches are etched in the dielectric layer using the hardmask layer such that the trenches have shallower portions and deeper portions alternating along a length of the trench. A conductor is deposited in the trenches such that crenulated conductive lines are formed having different depths periodically disposed along the length of the conductive line.
摘要翻译： 用于形成齿形导体的方法和具有齿形导体的器件包括在介电层上形成硬掩模层，并对硬掩模层进行构图。 使用硬掩模层在电介质层中蚀刻沟槽，使得沟槽具有沿着沟槽的长度交替的较浅部分和较深部分。 导体沉积在沟槽中，使得形成具有沿着导电线的长度周期性地设置的不同深度的锯齿形导电线。
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2.发明申请INTERCONNECT STRUCTURE WITH A PLANAR INTERFACE BETWEEN A SELECTIVE CONDUCTIVE CAP AND A DIELECTRIC CAP LAYER 有权与选择性导电盖和电介质层之间的平面界面的互连结构公开(公告)号：US20120068344A1
公开(公告)日：2012-03-22
申请号：US12887010
申请日：2010-09-21
申请人： Griselda Bonilla , Lawrence A. Clevenger , Elbert E. Huang , Satyanarayana V. Nitta , Shom Ponoth
发明人： Griselda Bonilla , Lawrence A. Clevenger , Elbert E. Huang , Satyanarayana V. Nitta , Shom Ponoth
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/5329 , H01L21/28562 , H01L21/288 , H01L21/76825 , H01L21/76826 , H01L21/76834 , H01L21/76835 , H01L21/76849 , H01L21/76861 , H01L21/76862 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.
摘要翻译： 选择性导电盖通过对金属互连结构的暴露的下面的电介质表面可选择的化学镀层沉积在金属线的暴露的金属表面上。 介电材料层沉积在选择性导电盖和暴露的下面的介质层上，而不需要预清洗。 介电材料层被平坦化以形成与选择性导电帽的最顶面共面的水平平面。 执行预清洁，并且在选择性导电盖和介电材料层的平坦化表面上沉积电介质盖层。 由于包括由预清洗层损坏的表面的界面垂直偏离金属线的最上表面，所以金属线中的金属沿着界面的电迁移减少或消除。
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3.发明授权Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer 有权互连结构与选择性导电盖和电介质盖层之间的平面界面公开(公告)号：US08809183B2
公开(公告)日：2014-08-19
申请号：US12887010
申请日：2010-09-21
申请人： Griselda Bonilla , Lawrence A. Clevenger , Elbert E. Huang , Satyanarayana V. Nitta , Shom Ponoth
发明人： Griselda Bonilla , Lawrence A. Clevenger , Elbert E. Huang , Satyanarayana V. Nitta , Shom Ponoth
IPC分类号： H01L21/4763
CPC分类号： H01L23/5329 , H01L21/28562 , H01L21/288 , H01L21/76825 , H01L21/76826 , H01L21/76834 , H01L21/76835 , H01L21/76849 , H01L21/76861 , H01L21/76862 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.
摘要翻译： 选择性导电盖通过对金属互连结构的暴露的下面的电介质表面可选择的化学镀层沉积在金属线的暴露的金属表面上。 介电材料层沉积在选择性导电盖和暴露的下面的介质层上，而不需要预清洗。 介电材料层被平坦化以形成与选择性导电帽的最顶面共面的水平平面。 执行预清洁，并且在选择性导电盖和介电材料层的平坦化表面上沉积电介质盖层。 由于包括由预清洗层损坏的表面的界面垂直偏离金属线的最上表面，所以金属线中的金属沿着界面的电迁移减少或消除。
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4.发明授权公开(公告)号：US08421239B2
公开(公告)日：2013-04-16
申请号：US12724903
申请日：2010-03-16
IPC分类号： H01L29/40
CPC分类号： H01L23/5283 , H01L21/31144 , H01L21/76804 , H01L21/76816 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method for forming crenulated conductors and a device having crenulated conductors includes forming a hardmask layer on a dielectric layer, and patterning the hardmask layer. Trenches are etched in the dielectric layer using the hardmask layer such that the trenches have shallower portions and deeper portions alternating along a length of the trench. A conductor is deposited in the trenches such that crenulated conductive lines are formed having different depths periodically disposed along the length of the conductive line.
摘要翻译： 用于形成齿形导体的方法和具有齿形导体的器件包括在介电层上形成硬掩模层，并对硬掩模层进行构图。 使用硬掩模层在电介质层中蚀刻沟槽，使得沟槽具有沿着沟槽的长度交替的较浅部分和较深部分。 导体沉积在沟槽中，使得形成具有沿着导电线的长度周期性地设置的不同深度的锯齿形导电线。
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公开(公告)号：US20130009282A1
公开(公告)日：2013-01-10
申请号：US13614524
申请日：2012-09-13
申请人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
发明人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
IPC分类号： H01L29/06
CPC分类号： H05K1/0216 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76852 , H05K1/0298 , H05K1/03 , H05K2201/0707 , H05K2201/09063
摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.
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公开(公告)号：US08288268B2
公开(公告)日：2012-10-16
申请号：US12770254
申请日：2010-04-29
申请人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
发明人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
IPC分类号： H01L29/40 , H01L21/4763
CPC分类号： H05K1/0216 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76852 , H05K1/0298 , H05K1/03 , H05K2201/0707 , H05K2201/09063
摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.
摘要翻译： 微电子结构和微电子结构的制造方法提供插入在多个导体层之间的多个空隙。 多个空隙也位于衬垫层和层间电介质层之间。 空隙提供了微电子结构的增强的电性能。
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公开(公告)号：US20110266682A1
公开(公告)日：2011-11-03
申请号：US12770254
申请日：2010-04-29
申请人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
发明人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
IPC分类号： H01L29/40 , H01L21/4763
CPC分类号： H05K1/0216 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76852 , H05K1/0298 , H05K1/03 , H05K2201/0707 , H05K2201/09063
摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.
摘要翻译： 微电子结构和微电子结构的制造方法提供插入在多个导体层之间的多个空隙。 多个空隙也位于衬垫层和层间电介质层之间。 空隙提供了微电子结构的增强的电性能。
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公开(公告)号：US09105693B2
公开(公告)日：2015-08-11
申请号：US13614563
申请日：2012-09-13
申请人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
发明人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
IPC分类号： H01L29/40 , H01L21/4763 , H01L21/768
CPC分类号： H05K1/0216 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76852 , H05K1/0298 , H05K1/03 , H05K2201/0707 , H05K2201/09063
摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.
摘要翻译： 微电子结构和微电子结构的制造方法提供插入在多个导体层之间的多个空隙。 多个空隙也位于衬垫层和层间电介质层之间。 空隙提供了微电子结构的增强的电性能。
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公开(公告)号：US07943480B2
公开(公告)日：2011-05-17
申请号：US12029800
申请日：2008-02-12
申请人： Daniel C. Edelstein , Nicholas C. M. Fuller , David V. Horak , Elbert E. Huang , Wai-Kin Li , Anthony D. Lisi , Satyanarayana V. Nitta , Shom Ponoth
发明人： Daniel C. Edelstein , Nicholas C. M. Fuller , David V. Horak , Elbert E. Huang , Wai-Kin Li , Anthony D. Lisi , Satyanarayana V. Nitta , Shom Ponoth
IPC分类号： H01L23/00
CPC分类号： H01L21/7682 , H01L21/0273 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.
摘要翻译： 公开了亚光刻尺寸气隙形成和相关结构。 在一个实施例中，一种方法包括在衬底上形成包括互连的介质层; 在电介质层上沉积盖层; 在所述盖层上沉积光致抗蚀剂; 图案化光致抗蚀剂以包括最多部分地覆盖互连的第一沟槽图案; 在所述第一沟槽图案内形成间隔物以形成具有亚光刻尺寸的第二沟槽图案; 将所述第二沟槽图案转移到所述覆盖层中并进入所述互连之间的所述介电层; 并且通过夹住介电层中的沟槽而沉积另一介质层以形成气隙。
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公开(公告)号：US09059251B2
公开(公告)日：2015-06-16
申请号：US13614524
申请日：2012-09-13
申请人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
发明人： Daniel C. Edelstein , David V. Horak , Elbert E. Huang , Satyanarayana V. Nitta , Takeshi Nogami , Shom Ponoth , Terry A. Spooner
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/768
CPC分类号： H05K1/0216 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76852 , H05K1/0298 , H05K1/03 , H05K2201/0707 , H05K2201/09063
摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.
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