发明申请
US20110239021A1 Memory calibration method and apparatus for power reduction during flash operation
有权
闪存操作期间功率降低的存储器校准方法和设备
- 专利标题: Memory calibration method and apparatus for power reduction during flash operation
- 专利标题(中): 闪存操作期间功率降低的存储器校准方法和设备
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申请号: US13012299申请日: 2011-01-24
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公开(公告)号: US20110239021A1公开(公告)日: 2011-09-29
- 发明人: Rex Weldon Vedder , Bradford Edwin Golson , Michael Joseph Peters
- 申请人: Rex Weldon Vedder , Bradford Edwin Golson , Michael Joseph Peters
- 申请人地址: US CO Longmont
- 专利权人: DOT HILL SYSTEMS CORPORATION
- 当前专利权人: DOT HILL SYSTEMS CORPORATION
- 当前专利权人地址: US CO Longmont
- 主分类号: G06F1/32
- IPC分类号: G06F1/32
摘要:
A method for providing reduced power consumption in a computer memory system is provided. The method includes calibrating, by a processor, a volatile memory of the computer memory system at a first and a second operating speed, where the second operating speed is higher than the first operating speed. The method also includes operating, by a memory controller coupled to the processor and the volatile memory, the volatile memory at the second operating speed if a main power source provides power to the computer memory system. The method further includes operating, by the memory controller, the volatile memory at the first operating speed if a backup power source provides power to the memory controller and the volatile memory. The backup power source provides power to the memory controller and the volatile memory when there is a loss of main power to the computer memory system.
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