- 专利标题: SEMICONDUCTOR DEVICE
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申请号: US13179163申请日: 2011-07-08
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公开(公告)号: US20110266631A1公开(公告)日: 2011-11-03
- 发明人: Naozumi MORINO , Atsushi HIRAIWA , Kazutoshi OKU , Toshiaki ITO , Motoshige IGARASHI , Takayuki SASAKI , Masao SUGIYAMA , Hiroshi YANAGITA , Shinichi WATARAI
- 申请人: Naozumi MORINO , Atsushi HIRAIWA , Kazutoshi OKU , Toshiaki ITO , Motoshige IGARASHI , Takayuki SASAKI , Masao SUGIYAMA , Hiroshi YANAGITA , Shinichi WATARAI
- 专利权人: RENESAS ELECTRONICS CORPORATION
- 当前专利权人: RENESAS ELECTRONICS CORPORATION
- 优先权: JP2008-123634 20080509
- 主分类号: H01L27/092
- IPC分类号: H01L27/092
摘要:
There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
公开/授权文献
- US08110878B2 Semiconductor device having a plurality of shallow wells 公开/授权日:2012-02-07