公开(公告)号：US07897467B2

公开(公告)日：2011-03-01

申请号：US12784876

申请日：2010-05-21

申请人： Satoshi Sakai ,  Atsushi Hiraiwa ,  Satoshi Yamamoto

发明人： Satoshi Sakai ,  Atsushi Hiraiwa ,  Satoshi Yamamoto

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823462 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878

摘要： After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10) is formed on the semiconductor substrate (1). Consequently, two kinds of gate insulation films, namely, a gate insulation film (12) comprised of stacked film of high dielectric constant insulation film (10) and silicon oxide film (9) and gate insulation film (11) comprised of the high dielectric constant insulation film (10) are formed on the semiconductor substrate (1).

摘要翻译： 在半导体基板（1）的表面上形成氧化硅膜（9）之后，使用稀释的HF除去形成有效厚度小的栅极绝缘膜的区域中的氧化硅膜（9） 在半导体衬底（1）上形成高介电常数绝缘膜（10）。 因此，由高介电常数绝缘膜（10）和氧化硅膜（9）构成的栅极绝缘膜（12）和栅极绝缘膜（12）构成的两种栅极绝缘膜由高介电常数 在半导体衬底（1）上形成恒定绝缘膜（10）。

公开(公告)号：US20110024847A1

公开(公告)日：2011-02-03

申请号：US12901858

申请日：2010-10-11

申请人： NAOZUMI MORINO ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

发明人： NAOZUMI MORINO ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

IPC分类号： H01L27/092

CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

公开(公告)号：US07821076B2

公开(公告)日：2010-10-26

申请号：US12422278

申请日：2009-04-12

申请人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

发明人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62

CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

公开(公告)号：US5936726A

公开(公告)日：1999-08-10

申请号：US913392

申请日：1997-09-09

申请人： Kazuo Takeda ,  Hidetsugu Ishida ,  Atsushi Hiraiwa

发明人： Kazuo Takeda ,  Hidetsugu Ishida ,  Atsushi Hiraiwa

IPC分类号： G01N21/94 ,  G01N21/00

CPC分类号： G01N21/94

摘要： An inspection method and apparatus for discriminating the foreign particles on the surface of a sample from the foreign particles or defects within the sample, and a semiconductor-device producing method using the inspection method and apparatus. The inspection apparatus includes a light source, a first optical system that causes the light from the source to be directed to the sample, a second optical system for condensing the light coming back from the sample, a polarizing prism for separating the condensed light into polarized components, and optical detectors, for detecting the polarized components. The two optical systems, are arranged for their optical axes to make an angle of 50.degree. to 120.degree. relative to each other. The foreign particles on the surface of the sample and the foreign particles or defects within the sample are respectively discriminated from each other as side scattered light and backward scattered light by utilizing the difference between the intensity ratios of the polarized light components.

摘要翻译： PCT No.PCT / JP95 / 00398 Sec。 371日期1997年9月9日 102（e）日期1997年9月9日PCT 1996年3月10日PCT公布。 第WO96 / 28721号公报 日期1996年9月19日一种用于鉴别样品表面上的异物与样品中的异物或缺陷的检查方法和装置，以及使用检查方法和装置的半导体器件制造方法。 检查装置包括光源，使来自源的光被引导到样本的第一光学系统，用于聚集从样品回来的光的第二光学系统，用于将聚光分离成偏振光的偏光棱镜 组件和光学检测器，用于检测偏振分量。 两个光学系统被布置成使它们的光轴相对于彼此成50°到120°的角度。 通过利用偏振光分量的强度比之间的差异，将样品表面上的杂质颗粒和样品中的异物或缺陷分别彼此区分为侧向散射光和反向散射光。

公开(公告)号：US5466621A

公开(公告)日：1995-11-14

申请号：US141027

申请日：1993-10-25

申请人： Dai Hisamoto ,  Toru Kaga ,  Shinichiro Kimura ,  Masahiro Moniwa ,  Haruhiko Tanaka ,  Atsushi Hiraiwa ,  Eiji Takeda

发明人： Dai Hisamoto ,  Toru Kaga ,  Shinichiro Kimura ,  Masahiro Moniwa ,  Haruhiko Tanaka ,  Atsushi Hiraiwa ,  Eiji Takeda

IPC分类号： H01L21/336 ,  H01L21/339 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/108 ,  H01L27/11 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L29/785 ,  H01L21/76264 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/10808 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/1108 ,  H01L29/1062 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66954 ,  H01L29/78654 ,  H01L21/76278 ,  Y10S148/014

摘要： A semiconductor device such as FET or charge coupled device, having a channel or a charge coupled portion provided in a thin semiconductor layer which is nearly perpendicular to the substrate and to which the necessary electrode such as the gate electrode and the necessary insulating layer are added can maintain the necessary amount of electric current by securing the height of the semiconductor layer and also can have its plane size reduced minutely. Further, the semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics.

摘要翻译： 一种诸如FET或电荷耦合器件的半导体器件，其具有设置在薄半导体层中的沟道或电荷耦合部分，该半导体层几乎垂直于衬底并且添加诸如栅电极和必需绝缘层的必需电极 可以通过确保半导体层的高度来保持必要的电流量，并且还可以使其平面尺寸微小地减小。 此外，使用上述半导体器件的半导体存储器件适合于高集成度并且具有优异的电特性。

公开(公告)号：US5153685A

公开(公告)日：1992-10-06

申请号：US246514

申请日：1988-09-19

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/105 ,  H01L27/10808

摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. In a fifth aspect, the capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. In sixth and seventh aspects, wiring is provided. In the sixth aspect, an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; in the seventh aspect, a refractory metal, or a refractory metal silicide QSI.sub.x, where Q is a refractory metal and 0

摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在诸如DRAM的半导体衬底之上的电容器元件。 在本发明的第一方面中，电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 在第二方面，Y选择信号线与电容器元件的下电极层重叠。 在第三方面中，通过用于沟道阻挡区域的杂质的扩散，形成至少在电容器元件连接的开关MISFET的半导体区域下方的势垒层。 在第四方面中，电容器元件的电介质膜与其上的电容器电极层共同扩展。 在第五方面中，电容器电介质膜是其上具有氧化硅层的氮化硅膜，通过在高压下氧化氮化硅的表面层而形成氧化硅层。 在第六和第七方面中，提供了布线。 在第六方面中，在相同的真空溅射室中通过溅射形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 在第七方面中，将含有添加元素（例如Cu）的铝配线用作难熔金属或难熔金属硅化物QSIx（其中Q为难熔金属且0

公开(公告)号：US5091761A

公开(公告)日：1992-02-25

申请号：US384821

申请日：1989-07-25

申请人： Atsushi Hiraiwa ,  Shinichiro Kimura ,  Toshiyuki Mine ,  Takashi Kobayashi ,  Tokuo Kure ,  Shinpei Iijima ,  Jiro Yugami

发明人： Atsushi Hiraiwa ,  Shinichiro Kimura ,  Toshiyuki Mine ,  Takashi Kobayashi ,  Tokuo Kure ,  Shinpei Iijima ,  Jiro Yugami

IPC分类号： H01L27/108

CPC分类号： H01L27/10808

摘要： Disclosed is a semiconductor device including a charge storage capacitor having a storage electrode which is electrically connected to a switching transistor through a contact hole provided in an insulator and which has a greater film thickness than the radius of the contact hole, at least a part of the storage electrode being disposed above a data line. It is possible to reduce the memory cell area while preventing lowering in the capacitance, and thus realize high density and high integration of semiconductor devices.

摘要翻译： 公开了一种半导体器件，包括具有存储电极的电荷存储电容器，该存储电极通过设置在绝缘体中的接触孔与开关晶体管电连接并且具有比接触孔的半径更大的膜厚度，至少部分 所述存储电极设置在数据线的上方。 可以在防止电容降低的同时减小存储单元面积，从而实现半导体器件的高密度和高集成度。

公开(公告)号：US4365264A

公开(公告)日：1982-12-21

申请号：US265167

申请日：1981-05-19

申请人： Kiichiro Mukai ,  Seiki Harada ,  Shin-ichi Muramatsu ,  Atsushi Hiraiwa ,  Shigeru Takahashi ,  Katsuhisa Usami ,  Seiichi Iwata ,  Satoru Ito ,  Takeo Yoshimi

发明人： Kiichiro Mukai ,  Seiki Harada ,  Shin-ichi Muramatsu ,  Atsushi Hiraiwa ,  Shigeru Takahashi ,  Katsuhisa Usami ,  Seiichi Iwata ,  Satoru Ito ,  Takeo Yoshimi

IPC分类号： H01L21/768 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522 ,  H01L29/34

CPC分类号： H01L21/316 ,  H01L21/312 ,  H01L21/3185 ,  H01L23/291 ,  H01L24/05 ,  H01L2924/12044 ,  H01L2924/181

摘要： A semiconductor device has a passivation layer disposed on a semiconductor body having at least one circuit element therein. This layer is made of a silicon nitride material containing 0.8-5.9 weight-% of H, together with 61-70 weight-% of Si, 25-37 weight-% of N and up to 0.6 weight-% of O and has a density of 2.9-3.05 gr/cm.sup.3.

摘要翻译： 半导体器件具有设置在其中具有至少一个电路元件的半导体本体上的钝化层。 该层由含有0.8-5.9重量％的H，以及61-70重量％的Si，25-37重量％的N和至多0.6重量％的O的氮化硅材料制成，并且具有 密度2.9-3.05gr / cm3。

公开(公告)号：US07741677B2

公开(公告)日：2010-06-22

申请号：US12486944

申请日：2009-06-18

申请人： Satoshi Sakai ,  Atsushi Hiraiwa ,  Satoshi Yamamoto

发明人： Satoshi Sakai ,  Atsushi Hiraiwa ,  Satoshi Yamamoto

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/113

CPC分类号： H01L21/823462 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878

摘要： After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10) is formed on the semiconductor substrate (1). Consequently, two kinds of gate insulation films, namely, a gate insulation film (12) comprised of stacked film of high dielectric constant insulation film (10) and silicon oxide film (9) and gate insulation film (11) comprised of the high dielectric constant insulation film (10) are formed on the semiconductor substrate (1).

摘要翻译： 在半导体基板（1）的表面上形成氧化硅膜（9）之后，使用稀释的HF除去形成有效厚度小的栅极绝缘膜的区域中的氧化硅膜（9） 在半导体衬底（1）上形成高介电常数绝缘膜（10）。 因此，由高介电常数绝缘膜（10）和氧化硅膜（9）构成的栅极绝缘膜（12）和栅极绝缘膜（12）构成的两种栅极绝缘膜由高介电常数 在半导体衬底（1）上形成恒定绝缘膜（10）。

公开(公告)号：US06821854B2

公开(公告)日：2004-11-23

申请号：US10211262

申请日：2002-08-05

申请人： Takayuki Kanda ,  Atsushi Hiraiwa ,  Norio Suzuki ,  Satoshi Sakai ,  Shuji Ikeda ,  Yasuko Yoshida ,  Shinichi Horibe

发明人： Takayuki Kanda ,  Atsushi Hiraiwa ,  Norio Suzuki ,  Satoshi Sakai ,  Shuji Ikeda ,  Yasuko Yoshida ,  Shinichi Horibe

IPC分类号： H01L218234

CPC分类号： H01L21/823878 ,  H01L21/823857

摘要： A protection film is formed on a silicon oxide film 6 formed on the surface of a semiconductor substrate, a silicon oxide film is removed from a region where a thin gate-insulating film is to be formed by using, as a mask, a photoresist pattern that covers a region where a thick gate-insulating film is to be formed, and, then, the photoresist pattern is removed followed by washing. Then, the semiconductor substrate is heat-oxidized or a film is deposited thereon to form gate-insulating films having different thicknesses.

摘要翻译： 在形成于半导体基板的表面的氧化硅膜6上形成保护膜，利用光刻胶图案作为掩模，从要形成薄栅极绝缘膜的区域去除氧化硅膜 覆盖要形成厚栅极绝缘膜的区域，然后去除光致抗蚀剂图案，然后洗涤。 然后，半导体衬底被热氧化或在其上沉积膜以形成具有不同厚度的栅极绝缘膜。