A three-dimensional (“3D”) image display includes a signal controller which receives two-dimensional (“2D”) image information and 3D image information and generates control signals based on the 2D image information and the 3D image information, a clock generator which receives the control signals from the signal controller and generates a first clock signal corresponding to the 3D image information and a second clock signal corresponding to the 2D image information, and a gate driver which generates a gate-on voltage based on at least one of the first clock signal and the second clock signal, where a frequency of the second clock signal is lower than a frequency of the first clock signal and an amplitude of the second clock signal is less than an amplitude of the first clock signal.