A high density, asymmetric, butted junction CMOS inverter, formed on an SOI substrate, may include: an asymmetric p-FET that includes a halo implant on only a source side of the p-FET; an asymmetric n-FET that includes a halo implant on only a source side of the n-FET; and a butted junction comprising an area of said SOI substrate where a drain region of the asymmetric n-FET and a drain region of the asymmetric p-FET are in direct physical contact. Asymmetric halo implants may be formed by a sequential process of covering a first FET of the CMOS inverter with an ion-absorbing structure and applying angled ion radiation to only the source side of the second FET, removing the ion-absorbing structure, covering the first FET with a second ion-absorbing structure, and applying angled ion radiation to only the source side of the second FET. A layout display of CMOS integrated circuit may require one ground rule for the high density, asymmetric butted junction CMOS inverter and another ground rule for other CMOS circuits.