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    Integrated circuit structure incorporating one or more asymmetric field effect transistors as power gates for an electronic circuit with stacked symmetric field effect transistors
    2.
    发明授权
    Integrated circuit structure incorporating one or more asymmetric field effect transistors as power gates for an electronic circuit with stacked symmetric field effect transistors 有权
    集成电路结构，其包括一个或多个不对称场效应晶体管作为具有堆叠对称场效应晶体管的电子电路的功率门

    公开(公告)号：US08941180B2

    公开(公告)日：2015-01-27

    申请号：US13044872

    申请日：2011-03-10

    Applicant: Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    Inventor： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    IPC: H01L27/02 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/8238

    CPC classification number: H01L27/1203 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/78624

    Abstract: Disclosed is an integrated circuit having an asymmetric FET as a power gate for an electronic circuit, which has at least two stacked symmetric field effect transistors. The asymmetric FET has an asymmetric halo configuration (i.e., a single source-side halo or a source-side halo with a higher dopant concentration than a drain-side halo) and an asymmetric source/drain extension configuration (i.e., the source extension can be overlapped to a greater extent by the gate structure than the drain extension and/or the source extension can have a higher dopant concentration than the drain extension). As a result, the asymmetric FET has a low off current. In operation, the asymmetric FET is turned off when the electronic circuit is placed in a standby state and, due to the low off current (Ioff), effectively reduces standby leakage current from the electronic circuit. Additionally, avoiding the use of stacked asymmetric field effect transistors within the electronic circuit itself prevents performance degradation due to reduced linear drain current (Idlin).

    Abstract translation: 公开了具有不对称FET作为电子电路的功率门的集成电路，其具有至少两个堆叠的对称场效应晶体管。 非对称FET具有不对称的卤素配置（即，具有比漏极侧卤素更高的掺杂剂浓度的单个源极卤素或源极卤素）和非对称源极/漏极延伸配置（即，源极延伸可以 通过栅极结构比漏极延伸更大程度地重叠和/或源极延伸可以具有比漏极延伸更高的掺杂剂浓度）。 结果，不对称FET具有低截止电流。 在操作中，当电子电路处于待机状态时，不对称FET被关闭，并且由于低关断电流（Ioff），有效地减少了来自电子电路的待机漏电流。 另外，避免使用电子电路内的层叠的非对称场效应晶体管本身可以防止由于线性漏极电流（Idlin）的降低导致的性能劣化。

    Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening
    3.
    发明授权
    Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening 有权
    毯子短通道卷起植入物，具有通过图案化开口的非角度长通道补偿植入物

    公开(公告)号：US08900954B2

    公开(公告)日：2014-12-02

    申请号：US13289051

    申请日：2011-11-04

    Applicant: James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    Inventor： James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    IPC: H01L29/772 ,  H01L21/336 ,  H01L21/28 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265

    CPC classification number: H01L29/1041 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28026 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66537 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/78

    Abstract: A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.

    Abstract translation: 一种形成将衬底植入衬底的结构的方法，在衬底上图案掩模（具有暴露衬底的沟道区的至少一个开口），并在掩模上形成共形电介质层并使开口 。 保形介电层覆盖衬底的沟道区。 该方法还在保形电介质层上形成共形栅极金属层，通过共形栅极金属层和共形绝缘层将补偿注入植入衬底的沟道区，并在共形栅极金属层上形成栅极导体。 此外，该方法去除掩模以在衬底上留下栅极堆叠，在栅极堆叠上形成侧壁间隔物，然后在衬底中部分地在侧壁间隔物下方形成源极/漏极区域。

    Field effect transistor and a method of forming the transistor
    4.
    发明授权
    Field effect transistor and a method of forming the transistor 失效
    场效应晶体管和形成晶体管的方法

    公开(公告)号：US08759916B2

    公开(公告)日：2014-06-24

    申请号：US13359615

    申请日：2012-01-27

    Applicant: Andres Bryant ,  Edward J. Nowak

    Inventor： Andres Bryant ,  Edward J. Nowak

    IPC: H01L29/78

    CPC classification number: H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78621 ,  H01L29/78684

    Abstract: Disclosed are embodiments of a metal oxide semiconductor field effect transistor (MOSFET) structure and a method of forming the structure. The structure incorporates source/drain regions and a channel region between the source/drain regions. The source/drain regions can comprise silicon, which has high diffusivity to the source/drain dopant. The channel region can comprise a silicon alloy selected for optimal charge carrier mobility and band energy and for its low source/drain dopant diffusivity. During processing, the source/drain dopant can diffuse into the edge portions of the channel region. However, due to the low diffusivity of the silicon alloy to the source/drain dopant, the dopant does not diffuse deep into channel region. Thus, the edge portions of the silicon alloy channel region can have essentially the same dopant profile as the source/drain regions, but a different dopant profile than the center portion of the silicon alloy channel region.

    Abstract translation: 公开了金属氧化物半导体场效应晶体管（MOSFET）结构的实施例和形成该结构的方法。 该结构包括源极/漏极区域和源极/漏极区域之间的沟道区域。 源极/漏极区域可以包括对源极/漏极掺杂剂具有高扩散性的硅。 通道区域可以包括选择用于最佳电荷载流子迁移率和带能量以及其低源极/漏极掺杂剂扩散率的硅合金。 在处理期间，源/漏掺杂剂可以扩散到沟道区的边缘部分。 然而，由于硅合金对源极/漏极掺杂剂的低扩散性，掺杂剂不会深入沟道区域。 因此，硅合金沟道区域的边缘部分可以具有与源极/漏极区域基本相同的掺杂剂分布，但是与硅合金沟道区域的中心部分不同的掺杂剂分布。

    Integrated circuit device with series-connected field effect transistors and integrated voltage equalization and method of forming the device
    5.
    发明授权
    Integrated circuit device with series-connected field effect transistors and integrated voltage equalization and method of forming the device 失效
    具有串联场效应晶体管和集成电压均衡的集成电路器件及其形成方法

    公开(公告)号：US08507333B2

    公开(公告)日：2013-08-13

    申请号：US13455176

    申请日：2012-04-25

    Applicant: Andres Bryant ,  Edward J. Nowak

    Inventor： Andres Bryant ,  Edward J. Nowak

    IPC: H01L21/8224

    CPC classification number: H01L21/845 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211

    Abstract: Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body.

    Abstract translation: 公开了具有集成电压均衡的具有串联的平面或非平面场效应晶体管（FET）的集成电路器件和形成器件的方法。 串联连接的FET包括沿着半导体本体定位的门，以限定用于串联连接的FET的沟道区。 源极/漏极区域位于沟道区域的相对侧上的半导体本体内，使得相邻栅极之间的半导体本体的每个部分包括用于一个场效应晶体管的一个源极/漏极区域，用于与另一个场效应晶体管的另一个源极/漏极区域相邻接 。 集成电压均衡通过具有期望电阻的并行导电层实现，并且位于串联连接的FET上，使得其与栅极电隔离，但与半导体本体内的源极/漏极区域接触。

    FIELD EFFECT TRANSISTOR AND A METHOD OF FORMING THE TRANSISTOR
    6.
    发明申请
    FIELD EFFECT TRANSISTOR AND A METHOD OF FORMING THE TRANSISTOR 失效
    场效应晶体管和形成晶体管的方法

    公开(公告)号：US20130193481A1

    公开(公告)日：2013-08-01

    申请号：US13359615

    申请日：2012-01-27

    Applicant: Andres Bryant ,  Edward J. Nowak

    Inventor： Andres Bryant ,  Edward J. Nowak

    IPC: H01L29/78 ,  H01L21/335

    CPC classification number: H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78621 ,  H01L29/78684

    Abstract: Disclosed are embodiments of a metal oxide semiconductor field effect transistor (MOSFET) structure and a method of forming the structure. The structure incorporates source/drain regions and a channel region between the source/drain regions. The source/drain regions can comprise silicon, which has high diffusivity to the source/drain dopant. The channel region can comprise a silicon alloy selected for optimal charge carrier mobility and band energy and for its low source/drain dopant diffusivity. During processing, the source/drain dopant can diffuse into the edge portions of the channel region. However, due to the low diffusivity of the silicon alloy to the source/drain dopant, the dopant does not diffuse deep into channel region. Thus, the edge portions of the silicon alloy channel region can have essentially the same dopant profile as the source/drain regions, but a different dopant profile than the center portion of the silicon alloy channel region.

    Abstract translation: 公开了金属氧化物半导体场效应晶体管（MOSFET）结构的实施例和形成该结构的方法。 该结构包括源极/漏极区域和源极/漏极区域之间的沟道区域。 源极/漏极区域可以包括对源极/漏极掺杂剂具有高扩散性的硅。 通道区域可以包括选择用于最佳电荷载流子迁移率和带能量以及其低源极/漏极掺杂剂扩散率的硅合金。 在处理期间，源/漏掺杂剂可以扩散到沟道区的边缘部分。 然而，由于硅合金对源极/漏极掺杂剂的低扩散性，掺杂剂不会深入沟道区域。 因此，硅合金沟道区域的边缘部分可以具有与源极/漏极区域基本相同的掺杂剂分布，但是与硅合金沟道区域的中心部分不同的掺杂剂分布。

    Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit
    7.
    发明授权
    Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit 有权
    集成电路和采用集成工艺步骤形成集成电路的深沟槽隔离结构和深沟槽电容器结构的方法

    公开(公告)号：US08492820B2

    公开(公告)日：2013-07-23

    申请号：US13406664

    申请日：2012-02-28

    Applicant: Brent A. Anderson ,  Andres Bryant ,  Herbert L. Ho ,  Edward J. Nowak

    Inventor： Brent A. Anderson ,  Andres Bryant ,  Herbert L. Ho ,  Edward J. Nowak

    IPC: H01L29/94

    CPC classification number: H01L21/76224 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/66181

    Abstract: Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).

    Abstract translation: 公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。 形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。 在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。 因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。 在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

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