- 专利标题： Pattern verification method, program thereof, and manufacturing method of semiconductor device
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申请号： US13067567申请日： 2011-06-09
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公开(公告)号： US20110294263A1公开(公告)日： 2011-12-01
- 发明人: Ryuji Ogawa , Koji Hashimoto
- 申请人： Ryuji Ogawa , Koji Hashimoto
- 专利权人： KABUSHIKI KAISHA TOSHIBA
- 当前专利权人： KABUSHIKI KAISHA TOSHIBA
- 优先权： JP2005-244448 20050825
- 主分类号： H01L21/50
- IPC分类号： H01L21/50
摘要：
A verification method of an integrated circuit pattern includes extracting a pattern which is not greater than a preset pattern size, extracting a pattern edge as a target of lithography simulation from the extracted pattern, and performing the lithography simulation on the extracted pattern edge to verify the integrated circuit pattern.
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