A clock multiplying circuit includes: first and second inverters being ON/OFF-controlled by a positive- or negative-phase signal, respectively, of a first clock signal and including current source and current sync terminals; a capacitive element provided between output ends of the inverters; a current supplying unit increasing, if a frequency of the first clock signal increases, the control current and supplying the control current to the current source terminals of the inverters and outputting, from the current sync terminals of the inverters, a control current the same current amount as that of a control current to the current source terminal; a differential detecting unit receiving input of a potential difference signal between both electrodes of the capacitive element and generating a second clock signal having a phase difference of 90 degrees; and a multiplied-signal generating unit generating a double signal of the first clock signal on the basis of the clock signals.