A nonvolatile memory device including a cell array area in which a plurality of unit cells are arranged at least in one direction includes a plurality of memory transistors formed in the respective unit cells. Each memory transistor includes a gate pattern in which a tunnel insulating layer, a floating gate, an inter-gate insulating layer, and a control gate are laminated, and first and second junction areas arranged on opposite sides of the gate pattern, wherein the gate patterns are separated in the one direction by unit cells. The to nonvolatile memory device also includes a first conduction interconnection which extends in the one direction and is arranged in a position that overlaps the control gate and a plurality of first contacts, at least one of which is arranged for each of the control gates to connect the control gates and the first conduction interconnection.