公开(公告)号：US08866211B2

公开(公告)日：2014-10-21

申请号：US13076910

申请日：2011-03-31

申请人： Dong-Ryul Chang ,  Myoung-Kyu Park

发明人： Dong-Ryul Chang ,  Myoung-Kyu Park

IPC分类号： H01L29/788 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/11519

摘要： A nonvolatile memory device including a cell array area in which a plurality of unit cells are arranged at least in one direction includes a plurality of memory transistors formed in the respective unit cells. Each memory transistor includes a gate pattern in which a tunnel insulating layer, a floating gate, an inter-gate insulating layer, and a control gate are laminated, and first and second junction areas arranged on opposite sides of the gate pattern, wherein the gate patterns are separated in the one direction by unit cells. The nonvolatile memory device also includes a first conduction interconnection which extends in the one direction and is arranged in a position that overlaps the control gate and a plurality of first contacts, at least one of which is arranged for each of the control gates to connect the control gates and the first conduction interconnection.

摘要翻译： 包括其中多个单元电池至少沿一个方向排列的单元阵列区域的非易失性存储器件包括形成在各个单元电池中的多个存储晶体管。 每个存储晶体管包括其中层叠有隧道绝缘层，浮栅，栅极间绝缘层和控制栅极的栅极图案，以及布置在栅极图案的相对侧上的第一和第二接合区域，其中栅极 图案沿单位单元在一个方向上分离。 非易失性存储器件还包括在一个方向上延伸并且被布置在与控制栅极和多个第一触点重叠的位置的第一导电互连，其中至少一个布置用于每个控制栅极连接 控制门和第一导电互连。

公开(公告)号：US20090020844A1

公开(公告)日：2009-01-22

申请号：US12219336

申请日：2008-07-21

申请人： Myoung-kyu Park ,  Byung-sun Kim ,  Tae-jung Lee ,  Kee-in Bang

发明人： Myoung-kyu Park ,  Byung-sun Kim ,  Tae-jung Lee ,  Kee-in Bang

IPC分类号： H01L27/06

CPC分类号： H01L27/0814 ,  H01L27/0255

摘要： Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate.

摘要翻译： 提供具有片上型静电放电（ESD）保护电路的半导体器件及其制造方法。 片上型ESD保护电路可以包括具有与半导体衬底中的第二导电类型区域接触的第一导电类型区域的第一结二极管和具有布置在第一导电类型区域上并与第一导电类型区域接触的金属材料层的第一肖特基二极管 的半导体衬底。

公开(公告)号：US06403435B1

公开(公告)日：2002-06-11

申请号：US09722518

申请日：2000-11-28

申请人： Chang Yong Kang ,  Myoung Kyu Park

发明人： Chang Yong Kang ,  Myoung Kyu Park

IPC分类号： H01L21331

CPC分类号： H01L27/10894 ,  H01L21/76202 ,  H01L21/76224 ,  H01L27/10873 ,  H01L27/1203

摘要： A semiconductor device having a recessed silicon on insulator (SOI) structure includes an SOI substrate having a cell region, a peripheral region and a field region, the SOI substrate having a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer, a trench in the field region of the second semiconductor layer, a device isolation film within the trench, a peripheral region recessed in the second semiconductor layer, and an active semiconductor device on the cell region and the peripheral region of the second semiconductor layer.

摘要翻译： 具有凹陷绝缘体（SOI）结构的半导体器件包括具有单元区域，外围区域和场区域的SOI衬底，所述SOI衬底具有第一半导体层，第一半导体层上的绝缘层和 绝缘层上的第二半导体层，第二半导体层的场区域中的沟槽，沟槽内的器件隔离膜，凹陷在第二半导体层中的外围区域，以及在单元区域和外围区域上的有源半导体器件 第二半导体层的区域。

公开(公告)号：US08652911B2

公开(公告)日：2014-02-18

申请号：US13175332

申请日：2011-07-01

申请人： Kee-In Bang ,  Tae-Jung Lee ,  Myoung-Kyu Park

发明人： Kee-In Bang ,  Tae-Jung Lee ,  Myoung-Kyu Park

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L29/4238 ,  H01L21/28123 ,  H01L21/76232

摘要： A method of fabricating a semiconductor device includes forming a device isolation region on a semiconductor substrate to define an active region, forming a gate electrode on the active region and the device isolation region across the active region, and forming at least one gate electrode opening portion in the gate electrode so as to overlap an edge portion of the active region, wherein the gate electrode opening portion is simultaneously formed with the gate electrode.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成器件隔离区以限定有源区，在有源区上形成栅电极和穿过有源区的器件隔离区，并形成至少一个栅极电极开口部分 在栅电极中与有源区的边缘部重叠，其中栅电极开口部同时形成有栅电极。

公开(公告)号：US08143690B2

公开(公告)日：2012-03-27

申请号：US12219336

申请日：2008-07-21

申请人： Myoung-kyu Park ,  Byung-sun Kim ,  Tae-jung Lee ,  Kee-in Bang

发明人： Myoung-kyu Park ,  Byung-sun Kim ,  Tae-jung Lee ,  Kee-in Bang

IPC分类号： H01L27/06

CPC分类号： H01L27/0814 ,  H01L27/0255

摘要： Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate.

摘要翻译： 提供具有片上型静电放电（ESD）保护电路的半导体器件及其制造方法。 片上型ESD保护电路可以包括具有与半导体衬底中的第二导电类型区域接触的第一导电类型区域的第一结二极管和具有布置在第一导电类型区域上并与第一导电类型区域接触的金属材料层的第一肖特基二极管 的半导体衬底。

公开(公告)号：US20110305084A1

公开(公告)日：2011-12-15

申请号：US13050398

申请日：2011-03-17

申请人： Myoung-Kyu PARK

发明人： Myoung-Kyu PARK

IPC分类号： G11C14/00 ,  H01L29/94

CPC分类号： H01L29/7883 ,  G11C16/10 ,  H01L27/11519 ,  H01L27/11521

摘要： A non-volatile memory device includes; a first well having a first impurity concentration formed in a first region of a semiconductor substrate, a second well having a second impurity concentration different from the first impurity concentration formed in a second region of the semiconductor substrate, an access transistor with floating gate formed on the first region, and a control Metal Oxide Semiconductor (MOS) capacitor with one electrode formed on the second region. The floating gate and the one electrode are formed from respective portions of a unitary gate line extending across the first and second regions

摘要翻译： 非易失性存储装置包括： 具有形成在半导体衬底的第一区域中的第一杂质浓度的第一阱，具有与形成在半导体衬底的第二区域中的第一杂质浓度不同的第二杂质浓度的第二阱，形成有浮置栅极的存取晶体管，形成在 第一区域和形成在第二区域上的一个电极的控制金属氧化物半导体（MOS）电容器。 浮动栅极和一个电极由延伸穿过第一和第二区域的整体栅极线的相应部分形成

公开(公告)号：US20090290417A1

公开(公告)日：2009-11-26

申请号：US12348185

申请日：2009-01-02

申请人： Myoung-Kyu PARK ,  Byung-Sun KIM ,  Tae-Jung LEE ,  Dong-Ryul CHANG

发明人： Myoung-Kyu PARK ,  Byung-Sun KIM ,  Tae-Jung LEE ,  Dong-Ryul CHANG

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  G11C2216/10 ,  H01L27/11558

摘要： A nonvolatile memory device including a plurality of word lines; a plurality of bit lines intersecting the word lines; a plurality of memory cells corresponding to intersections of the word lines and the bit lines; a common control gate line commonly connected to the memory cells; and a common erasing gate line commonly connected to the memory cells.

摘要翻译： 一种包括多个字线的非易失性存储器件; 与字线相交的多个位线; 对应于字线和位线的交点的多个存储单元; 通常连接到存储器单元的公共控制栅极线; 以及通常连接到存储器单元的公共擦除栅极线。

公开(公告)号：US20100123245A1

公开(公告)日：2010-05-20

申请号：US12591110

申请日：2009-11-09

申请人： Tae-Jung Lee ,  Kee-In Bang ,  Myoung-Kyu Park ,  Kyoung-Eun Uhm

发明人： Tae-Jung Lee ,  Kee-In Bang ,  Myoung-Kyu Park ,  Kyoung-Eun Uhm

IPC分类号： H01L23/48

CPC分类号： H01L24/14 ,  H01L24/06 ,  H01L27/0251 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/14133 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A semiconductor integrated circuit device includes: an electrostatic discharge (ESD) impurity region formed in a substrate; a bump formed on the substrate; and a first wiring layer and a second wiring layer formed at the same level under the bump. The first and second wiring layers are separated from each other, and at least part of each of the first and second wiring layers are overlapped by the bump. The first wiring layer is electrically connected to the ESD impurity region and the bump, and the second wiring layer is insulated from the bump.

摘要翻译： 半导体集成电路器件包括：形成在衬底中的静电放电（ESD）杂质区; 形成在基板上的凸块; 以及形成在所述凸块下方的同一水平面上的第一布线层和第二布线层。 第一和第二布线层彼此分离，并且第一和第二布线层中的每一个的至少一部分由凸块重叠。 第一布线层电连接到ESD杂质区域和凸块，并且第二布线层与凸块绝缘。

公开(公告)号：US06410405B1

公开(公告)日：2002-06-25

申请号：US09895411

申请日：2001-07-02

申请人： Myoung Kyu Park

发明人： Myoung Kyu Park

IPC分类号： H01L21336

摘要： The present invention provides a method for forming a field oxide film on a semiconductor device. In particular, the present invention provides a method for forming a field oxide film on a semiconductor device using a silicon epitaxial layer to improve a Shallow Trench Isolation (STI) process.

公开(公告)号：US20120003805A1

公开(公告)日：2012-01-05

申请号：US13175332

申请日：2011-07-01

申请人： Kee-In Bang ,  Tae-Jung Lee ,  Myoung-Kyu Park

发明人： Kee-In Bang ,  Tae-Jung Lee ,  Myoung-Kyu Park

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L29/4238 ,  H01L21/28123 ,  H01L21/76232

摘要： A method of fabricating a semiconductor device includes forming a device isolation region on a semiconductor substrate to define an active region, forming a gate electrode on the active region and the device isolation region across the active region, and forming at least one gate electrode opening portion in the gate electrode so as to overlap an edge portion of the active region, wherein the gate electrode opening portion is simultaneously formed with the gate electrode.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成器件隔离区以限定有源区，在有源区上形成栅电极和穿过有源区的器件隔离区，并形成至少一个栅极电极开口部分 在栅电极中与有源区的边缘部重叠，其中栅电极开口部同时形成有栅电极。