发明申请
US20110309453A1 ELEVATION OF TRANSISTOR CHANNELS TO REDUCE IMPACT OF SHALLOW TRENCH ISOLATION ON TRANSISTOR PERFORMANCE
有权
晶体管通道的增加可以减少晶体管性能上的微分离分离的影响
- 专利标题： ELEVATION OF TRANSISTOR CHANNELS TO REDUCE IMPACT OF SHALLOW TRENCH ISOLATION ON TRANSISTOR PERFORMANCE
- 专利标题（中）： 晶体管通道的增加可以减少晶体管性能上的微分离分离的影响
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申请号： US13221747申请日： 2011-08-30
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公开(公告)号： US20110309453A1公开(公告)日： 2011-12-22
- 发明人: Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
- 申请人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
- 主分类号： H01L27/092
- IPC分类号： H01L27/092
摘要：
Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.