发明申请
- 专利标题: Methods of Manufacturing Power Semiconductor Devices with Trenched Shielded Split Gate Transistor
- 专利标题(中): 制造功率半导体器件与沟槽屏蔽分离栅晶体管的方法
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申请号: US13219229申请日: 2011-08-26
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公开(公告)号: US20110312138A1公开(公告)日: 2011-12-22
- 发明人: Joseph A. Yedinak , Nathan L. Kraft
- 申请人: Joseph A. Yedinak , Nathan L. Kraft
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
Methods of manufacturing power semiconductor devices include forming trenches in a substrate, depositing a shield oxide layer that conforms to the trenches, depositing a gate polysilicon layer into the trenches, etching the gate polysilicon layer so that the gate polysilicon layer is recessed in the trench, etching the shield oxide layer so that the shield oxide layer is recessed in the trench and lower than the gate polysilicon layer, depositing a layer of gate oxide across the top of the substrate, sidewalls of the trenches and troughs inside the trenches leaving a recess, depositing shield polysilicon in the recess, etching the shield polysilicon layer so that the shield polysilicon layer is recessed in the trench and higher than the gate polysilicon layer, forming a well region, and forming a source region. The well region can be formed with a −p-well implant. The source region can be performed with an n+ source implant.