发明申请
- 专利标题： LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME
- 专利标题（中）： 层状芯片包装及其制造方法
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申请号： US12822601申请日： 2010-06-24
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公开(公告)号： US20110316141A1公开(公告)日： 2011-12-29
- 发明人: Yoshitaka Sasaki , Hiroyuki Ito , Hiroshi Ikejima , Atsushi Iijima
- 申请人： Yoshitaka Sasaki , Hiroyuki Ito , Hiroshi Ikejima , Atsushi Iijima
- 申请人地址： CN Shatin US CA Milpitas
- 专利权人： SAE MAGNETICS(H.K) LTD.,HEADWAY TECHNOLOGIES, INC.
- 当前专利权人： SAE MAGNETICS(H.K) LTD.,HEADWAY TECHNOLOGIES, INC.
- 当前专利权人地址： CN Shatin US CA Milpitas
- 主分类号： H01L23/485
- IPC分类号： H01L23/485 ; H01L21/60 ; H01L21/822
摘要：
A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions stacked; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. The plurality of layer portions include a first-type layer portion and a second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, and a plurality of first-type electrodes that are connected to the semiconductor chip and the wiring. The second-type layer portion includes a defective semiconductor chip, and a plurality of second-type electrodes that are connected to the wiring and not to the semiconductor chip.
公开/授权文献
- US08421243B2 Layered chip package and method of manufacturing same 公开/授权日：2013-04-16
信息查询
IPC分类:
