发明申请
- 专利标题: Integrated Circuit Arrangement For Test Inputs
- 专利标题(中): 用于测试输入的集成电路布置
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申请号: US12822287申请日: 2010-06-24
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公开(公告)号: US20110320898A1公开(公告)日: 2011-12-29
- 发明人: Ulrich Baur , Lawrence D. Curley , Ronald J. Frishmuth , Ralf Ludewig , Ching L. Tong , Tobias Webel
- 申请人: Ulrich Baur , Lawrence D. Curley , Ronald J. Frishmuth , Ralf Ludewig , Ching L. Tong , Tobias Webel
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 主分类号: G01R31/3177
- IPC分类号: G01R31/3177 ; G06F11/25
摘要:
An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.
公开/授权文献
- US08479070B2 Integrated circuit arrangement for test inputs 公开/授权日:2013-07-02