摘要:
An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.
摘要:
An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.
摘要:
A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.
摘要:
Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch indicating the presence of the plurality of processor requests at the central point, establishing a sequential order of the plurality of processor requests, and processing the plurality of processor requests at the central point in the sequential order.
摘要:
A digital video encoder system having a motion estimation processor, and an interface to the motion estimation processor. The motion estimation processor includes a reference memory interface, and inverse quantization processor, an inverse discrete cosine transform processor, and a motion estimation processor unit including a hierarchal search unit. The motion estimation processor is utilized generating temporally compressed datastreams, that is, I-P and I-P-B datastreams.
摘要:
Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.
摘要:
Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.
摘要:
A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.
摘要:
Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch indicating the presence of the plurality of processor requests at the central point, establishing a sequential order of the plurality of processor requests, and processing the plurality of processor requests at the central point in the sequential order.
摘要:
A processing facility is provided for simultaneously receiving multiple streams of digital audio data and based thereon concurrently outputting both an unmixed digital audio signal and a mixed digital audio signal. The processing facility can be implemented, for example, within an audio decoder of a set top box. The facility includes receiving a first stream of digital audio data and a second stream of digital audio data, and outputting the first stream of digital audio data as an unmixed digital audio signal. Simultaneous therewith, the first stream of digital audio data and the second stream of digital audio data are digitally mixed and outputted as a mixed digital audio signal. If necessary, the second stream of digital audio data is redigitized based on a sample frequency of the first stream of digital audio data, and either or both the first stream and second stream of digital audio data are decoded prior to mixing.