发明申请
- 专利标题: CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF
- 专利标题(中): 芯片尺寸包装及其制造方法
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申请号: US12955613申请日: 2010-11-29
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公开(公告)号: US20120013006A1公开(公告)日: 2012-01-19
- 发明人: Chiang-Cheng Chang , Chien-Ping Huang , Chun-Chi Ke
- 申请人: Chiang-Cheng Chang , Chien-Ping Huang , Chun-Chi Ke
- 申请人地址: TW Taichung
- 专利权人: SILICONWARE PRECISION INDUSTRIES CO., LTD.
- 当前专利权人: SILICONWARE PRECISION INDUSTRIES CO., LTD.
- 当前专利权人地址: TW Taichung
- 优先权: TW099122934 20100713
- 主分类号: H01L23/485
- IPC分类号: H01L23/485 ; H01L21/786
摘要:
A fabrication method of a chip scale package is provided, which includes forming a protection layer on the active surface of a chip and fixing the inactive surface of the chip to a transparent carrier; performing a molding process; removing the protection layer from the chip and performing a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the wiring layer formed in the RDL process and the chip electrode pads and even waste product as a result. Further, the transparent carrier employed in the invention can be separated by laser and repetitively used in the process to help reduce the fabrication cost.
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