摘要:
A package structure includes a base body having a first encapsulant and a wiring layer embedded in and exposed from the first encapsulant. The wiring layer has a plurality of conductive traces and a plurality of first electrical contact pads. The first encapsulant has openings for exposing the first electrical contact pads, a chip electrically connected to the wiring layer, and a second encapsulant formed on the base body for covering the chip and the wiring layer, thereby providing an even surface for preventing the encapsulant from cracking when the chip is mounted.
摘要:
A fabrication method of a semiconductor package structure includes: patterning a metal plate having first and second surfaces; forming a dielectric layer on the metal plate; forming a metal layer on the first surface and the dielectric layer; forming metal pads on the second surface, the metal layer having a die pad and traces each having a bond pad; mounting a semiconductor chip on the die pad, followed by connecting electrically the semiconductor chip to the bond pads through bonding wires; forming an encapsulant to cover the semiconductor chip and the metal layer; removing portions of the metal plate not covered by the metal pads so as to form metal pillars; and performing a singulation process. The fabrication method is characterized by disposing traces with bond pads close to the die pad to shorten the bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging.
摘要:
A package structure having an MEMS element includes: a chip having at least an MEMS element and a plurality of first conductive pads; a lid disposed on the chip to cover the MEMS element and having a plurality of second conductive pads formed thereon; a plurality of bonding wires electrically connecting the first and second conductive pads; a plurality of first bumps disposed on the second conductive pads, respectively; an encapsulant formed on the chip to encapsulate the lid, the bonding wires, the first and second conductive pads and the first bumps while exposing the top surfaces of the first bumps; and a plurality of circuits formed on the encapsulant and electrically connecting to the exposed first bumps, thereby avoiding the conventional drawback of electrical connection failure caused by position deviation of bonding wires due to mold flow of the encapsulant.
摘要:
A fabrication method of a chip scale package is provided, which includes forming a protection layer on the active surface of a chip and fixing the inactive surface of the chip to a transparent carrier; performing a molding process; removing the protection layer from the chip and performing a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the wiring layer formed in the RDL process and the chip electrode pads and even waste product as a result. Further, the transparent carrier employed in the invention can be separated by laser and repetitively used in the process to help reduce the fabrication cost.
摘要:
A quad flat non-leaded (QFN) package structure with an electromagnetic interference (EMI) shielding function is proposed, including: a lead frame having a die pad, a plurality of supporting portions connecting to the die pad and a plurality of leads disposed around the periphery of the die pad without connecting to the die pad; a chip mounted on the die pad; bonding wires electrically connecting the chip and the leads; an encapsulant for encapsulating the chip, the bonding wires and the lead frame and exposing the side and bottom surfaces of the leads and the bottom surface of the die pad; and a shielding film disposed on the top and side surfaces of the encapsulant and electrically connecting to the supporting portions for shielding from EMI. A method of fabricating the package structure as described above is further proposed.
摘要:
A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process.
摘要:
An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.
摘要:
A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect.
摘要:
A conductive bump structure for a semiconductor device and a method for fabricating the same are provided. A metal bump is formed on an under bump metallurgy (UBM) structure electrically connected to and formed on a connection pad of the semiconductor device, wherein the metal bump is sized smaller than the UBM structure. Subsequently, a solder bump is mounted on the UBM structure and encapsulates the metal bump, so as to increase the bonding area and simultaneously allow the solder bump to be sufficiently wetted on the UBM structure to enhance bonding stress of the solder bump.
摘要:
A semiconductor device having conductive bumps and a fabrication method thereof are provided. The fabrication method mainly including steps of: providing a semiconductor substrate having a solder pad and a passivation layer formed thereon with a portion of the solder pads exposed from the passivation layer; disposing a first metal layer on the solder pad and a portion of the passivation layer around the solder pad; disposing a covering layer on the first metal layer and the passivation layer, and forming an aperture in the covering layer to expose a portion of the first metal layer, wherein a center of the aperture is deviated from that of the solder pad; deposing a metal pillar on the portion of the first metal layer; and deposing a solder material on an outer surface of the metal pillar for providing a better buffering effect.