发明申请
US20120017190A1 IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME
失效
实施和检查具有灵活的运动限制的电子电路和用于执行其的工具
- 专利标题： IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME
- 专利标题（中）： 实施和检查具有灵活的运动限制的电子电路和用于执行其的工具
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申请号： US12836274申请日： 2010-07-14
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公开(公告)号： US20120017190A1公开(公告)日： 2012-01-19
- 发明人: Alexander Tetelbaum , Joseph J. Jamann , Richard A. Laubhan , Bruce Zahn
- 申请人： Alexander Tetelbaum , Joseph J. Jamann , Richard A. Laubhan , Bruce Zahn
- 申请人地址： US CA Milpitas
- 专利权人： LSI Corporation
- 当前专利权人： LSI Corporation
- 当前专利权人地址： US CA Milpitas
- 主分类号： G06F9/455
- IPC分类号： G06F9/455 ; G06F17/50
摘要：
An apparatus and a method of generating a flexible ramptime limit for an electronic circuit, a computer program product that performs the same method, and a method of manufacturing an electronic circuit employing a flexible ramptime limit is disclosed. In one embodiment, the method for generating a flexible ramptime limit includes: (1) calculating a frequency based ramptime limit for the electronic circuit, (2) obtaining a library based ramptime limit for the electronic circuit, (3) determining a minimum ramptime limit between the frequency based ramptime limit and the library based ramptime limit and (4) selecting the minimum ramptime limit as the flexible ramptime limit.
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