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    Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the same
    1.
    发明授权
    Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the same 失效
    实施和检查具有灵活的ramptime限制的电子电路和执行相同的工具

    公开(公告)号：US08332792B2

    公开(公告)日：2012-12-11

    申请号：US12836274

    申请日：2010-07-14

    申请人： Alexander Tetelbaum ,  Joseph Jamann ,  Rich Laubhan ,  Bruce Zahn

    发明人： Alexander Tetelbaum ,  Joseph Jamann ,  Rich Laubhan ,  Bruce Zahn

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/505

    摘要： An apparatus and a method of generating a flexible ramptime limit for an electronic circuit, a computer program product that performs the same method, and a method of manufacturing an electronic circuit employing a flexible ramptime limit is disclosed. In one embodiment, the method for generating a flexible ramptime limit includes: (1) calculating a frequency based ramptime limit for the electronic circuit, (2) obtaining a library based ramptime limit for the electronic circuit, (3) determining a minimum ramptime limit between the frequency based ramptime limit and the library based ramptime limit and (4) selecting the minimum ramptime limit as the flexible ramptime limit.

    摘要翻译： 公开了一种生成电子电路的灵活的抵触限制的装置和方法，执行相同方法的计算机程序产品以及采用灵活的突发限制的电子电路的制造方法。 在一个实施例中，用于产生灵活的突发时间限制的方法包括：（1）计算电子电路的基于频率的抵触时间限制，（2）获得用于电子电路的基于库的抵扣限制，（3）确定最小的抵押限制 基于频率的ramptime限制和基于库的ramptime限制;（4）选择最小ramptime限制作为灵活的ramptime限制。

    SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION CONCURRENTLY IN MULTIPLE SCENARIOS TO REDUCE DYNAMIC POWER IN AN ELECTRONIC CIRCUIT AND AN APPARATUS INCORPORATING THE SAME
    2.
    发明申请
    SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION CONCURRENTLY IN MULTIPLE SCENARIOS TO REDUCE DYNAMIC POWER IN AN ELECTRONIC CIRCUIT AND AN APPARATUS INCORPORATING THE SAME 有权
    用于在多个场景中同时使用的信号质量时序分析信息的系统和方法，以减少电子电路中的动态功率和包含其中的装置

    公开(公告)号：US20120221995A1

    公开(公告)日：2012-08-30

    申请号：US13034167

    申请日：2011-02-24

    申请人： Bruce Zahn ,  James C. Parker ,  Benjamin Mbouombouo

    发明人： Bruce Zahn ,  James C. Parker ,  Benjamin Mbouombouo

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/505 ,  G06F2217/78 ,  G06F2217/84

    摘要： A dynamic power recovery system and method are disclosed herein. Additionally, an EDA tool and apparatus configured to perform dynamic power recovery are disclosed. In one embodiment, the system includes: (1) a power recovery module configured to carry out an instance of an initial power recovery process in each of multiple scenarios concurrently, the initial power recovery process including making first conditional downsizing of cells in at least one path in a circuit design with lower dynamic power cells and estimating a delay and a slack of the at least one path based on the first conditional downsizings and (2) a speed recovery module associated with the power recovery module and configured to carry out a speed recovery process in each of the multiple scenarios concurrently, the speed recovery process including determining whether the first conditional downsizings cause a timing violation with respect to the at least one path and making second conditional upsizings with higher dynamic power cells until the timing violation is removed.

    摘要翻译： 本文公开了动态功率恢复系统和方法。 此外，公开了一种被配置为执行动态功率恢复的EDA工具和装置。 在一个实施例中，系统包括：（1）功率恢复模块，被配置为在多个场景中同时执行初始功率恢复过程的一个实例，初始功率恢复过程包括在至少一个 在具有较低动态功率单元的电路设计中的路径，以及基于所述第一条件降序估计所述至少一个路径的延迟和松弛，以及（2）与所述功率恢复模块相关联的并且被配置为执行速度 所述速度恢复过程包括确定所述第一条件降序是否导致相对于所述至少一个路径的定时违反，并且使得具有较高动态功率单元的第二条件升高直到所述定时违反被去除。

    IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME
    3.
    发明申请
    IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME 失效
    实施和检查具有灵活的运动限制的电子电路和用于执行其的工具

    公开(公告)号：US20120017190A1

    公开(公告)日：2012-01-19

    申请号：US12836274

    申请日：2010-07-14

    申请人： Alexander Tetelbaum ,  Joseph J. Jamann ,  Richard A. Laubhan ,  Bruce Zahn

    发明人： Alexander Tetelbaum ,  Joseph J. Jamann ,  Richard A. Laubhan ,  Bruce Zahn

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/505

    摘要： An apparatus and a method of generating a flexible ramptime limit for an electronic circuit, a computer program product that performs the same method, and a method of manufacturing an electronic circuit employing a flexible ramptime limit is disclosed. In one embodiment, the method for generating a flexible ramptime limit includes: (1) calculating a frequency based ramptime limit for the electronic circuit, (2) obtaining a library based ramptime limit for the electronic circuit, (3) determining a minimum ramptime limit between the frequency based ramptime limit and the library based ramptime limit and (4) selecting the minimum ramptime limit as the flexible ramptime limit.

    摘要翻译： 公开了一种生成电子电路的灵活的抵触限制的装置和方法，执行相同方法的计算机程序产品以及采用灵活的突发限制的电子电路的制造方法。 在一个实施例中，用于产生灵活的突发时间限制的方法包括：（1）计算电子电路的基于频率的抵触时间限制，（2）获得用于电子电路的基于库的抵扣限制，（3）确定最小的抵押限制 基于频率的ramptime限制和基于库的ramptime限制;（4）选择最小ramptime限制作为灵活的ramptime限制。

    System and method for employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce dynamic power in an electronic circuit and an apparatus incorporating the same
    4.
    发明授权
    System and method for employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce dynamic power in an electronic circuit and an apparatus incorporating the same 有权
    在多种情况下同时采用签约质量时序分析信息以减少电子电路中的动态功率的系统和方法及其结合的装置

    公开(公告)号：US08713506B2

    公开(公告)日：2014-04-29

    申请号：US13034167

    申请日：2011-02-24

    申请人： Bruce Zahn ,  James C. Parker ,  Benjamin Mbouombouo

    发明人： Bruce Zahn ,  James C. Parker ,  Benjamin Mbouombouo

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/78 ,  G06F2217/84

    摘要： A dynamic power recovery system and method are disclosed herein. Additionally, an EDA tool and apparatus configured to perform dynamic power recovery are disclosed. In one embodiment, the system includes: (1) a power recovery module configured to carry out an instance of an initial power recovery process in each of multiple scenarios concurrently, the initial power recovery process including making first conditional downsizing of cells in at least one path in a circuit design with lower dynamic power cells and estimating a delay and a slack of the at least one path based on the first conditional downsizings and (2) a speed recovery module associated with the power recovery module and configured to carry out a speed recovery process in each of the multiple scenarios concurrently, the speed recovery process including determining whether the first conditional downsizings cause a timing violation with respect to the at least one path and making second conditional upsizings with higher dynamic power cells until the timing violation is removed.

    摘要翻译： 本文公开了动态功率恢复系统和方法。 此外，公开了一种被配置为执行动态功率恢复的EDA工具和装置。 在一个实施例中，系统包括：（1）功率恢复模块，被配置为在多个场景中同时执行初始功率恢复过程的一个实例，初始功率恢复过程包括在至少一个 在具有较低动态功率单元的电路设计中的路径，以及基于所述第一条件降序估计所述至少一个路径的延迟和松弛，以及（2）与所述功率恢复模块相关联的并且被配置为执行速度 所述速度恢复过程包括确定所述第一条件降序是否导致相对于所述至少一个路径的定时违反，并且使得具有较高动态功率单元的第二条件升高直到所述定时违反被去除。