Invention Application
- Patent Title: SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
- Patent Title (中): 半导体存储器件及其制造方法
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Application No.: US13187000Application Date: 2011-07-20
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Publication No.: US20120020158A1Publication Date: 2012-01-26
- Inventor: Tohru OZAKI , Mitsuhiro Noguchi , Hideaki Maekawa , Hiromitsu Mashita , Takafumi Taguchi , Kazuhito Kobayashi , Hidefumi Mukai , Hiroyuki Nitta
- Applicant: Tohru OZAKI , Mitsuhiro Noguchi , Hideaki Maekawa , Hiromitsu Mashita , Takafumi Taguchi , Kazuhito Kobayashi , Hidefumi Mukai , Hiroyuki Nitta
- Applicant Address: JP Tokyo
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Tokyo
- Priority: JP2010-164253 20100721
- Main IPC: G11C16/04
- IPC: G11C16/04 ; H01L21/78

Abstract:
A memory cell array includes memory strings arranged in a first direction. Word-lines and select gate lines extend in a second direction perpendicular to the first direction. The select gate line also extends in the second direction. The word-lines have a first line width in the first direction and arranged with a first distance therebetween. The select gate line includes a first interconnection in the first direction, the first interconnection having a second line width larger than the first line width, and a second interconnection extending from an end portion of the first interconnection, the second interconnection having a third line width the same as the first line width. A first word-line adjacent to the select gate line is arranged having a second distance to the second interconnection, the second distance being (4N+1) times the first distance (N being an integer of 1 or more).
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