发明申请
- 专利标题： CHIP PACKAGE AND FABRICATING METHOD THEREOF
- 专利标题（中）： 芯片包装及其制作方法
-
申请号： US12844590申请日： 2010-07-27
-
公开(公告)号： US20120025387A1公开(公告)日： 2012-02-02
- 发明人: Kuo-Ching CHANG , Wu-Cheng Kuo , Tzu-Han Lin
- 申请人： Kuo-Ching CHANG , Wu-Cheng Kuo , Tzu-Han Lin
- 主分类号： H01L23/492
- IPC分类号： H01L23/492 ; H01L21/50
摘要：
A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.
公开/授权文献
- US08399969B2 Chip package and fabricating method thereof 公开/授权日：2013-03-19
信息查询
IPC分类:
