发明申请
US20120034746A1 Methods of Fabricating MOS Transistors Having Recesses With Elevated Source/Drain Regions
有权
制造具有高的源极/漏极区域的凹槽的MOS晶体管的方法
- 专利标题： Methods of Fabricating MOS Transistors Having Recesses With Elevated Source/Drain Regions
- 专利标题（中）： 制造具有高的源极/漏极区域的凹槽的MOS晶体管的方法
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申请号： US13241311申请日： 2011-09-23
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公开(公告)号： US20120034746A1公开(公告)日： 2012-02-09
- 发明人: Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Deok-Hyung Lee , In-Soo Jung
- 申请人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Deok-Hyung Lee , In-Soo Jung
- 优先权： KR2003-45787 20030707
- 主分类号： H01L21/336
- IPC分类号： H01L21/336
摘要：
Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.