发明申请
US20120047478A1 Method For Estimating The Latency Time Of A Clock Tree In An Asic Design
失效
用于估计Asic设计中时钟树的延迟时间的方法
- 专利标题： Method For Estimating The Latency Time Of A Clock Tree In An Asic Design
- 专利标题（中）： 用于估计Asic设计中时钟树的延迟时间的方法
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申请号： US13031953申请日： 2011-02-22
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公开(公告)号： US20120047478A1公开(公告)日： 2012-02-23
- 发明人: Liang Ge , Gong Qiong Li , Suo Ming Pu , Chen Xu
- 申请人： Liang Ge , Gong Qiong Li , Suo Ming Pu , Chen Xu
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 优先权： CN201010117747.7 20100226
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
Estimating the latency time of the clock tree of an ASIC including: providing a netlist and a placement related to the clock tree of the ASIC; extracting a number of the load timing devices connected by the clock tree according to the netlist related to the clock tree; extracting a physical distribution area of the load timing devices connected by the clock tree according to the placement related to the clock tree; estimating a latency time of the clock tree according to the relationship between the number of the load timing devices, the physical distribution area of the load timing devices and latency time of the clock tree in design data related to the ASIC design.
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