公开(公告)号：US20170213480A1

公开(公告)日：2017-07-27

申请号：US15424070

申请日：2017-02-03

申请人： Mark B. Ratcliffe ,  Liang Ge ,  Alan Bao-Chan Dang

发明人： Mark B. Ratcliffe ,  Liang Ge ,  Alan Bao-Chan Dang

IPC分类号： G09B23/28 ,  G09B9/00

CPC分类号： G09B23/28 ,  G09B5/00 ,  G09B9/00

摘要： A method and system are presented for performing virtual surgery simulations. The computer system includes a processor and a memory. The method includes receiving user input from a user via a user interface. The user input includes input representing surgical operations or non-surgical invasive procedures. The method also includes processing the user input and utilizing the input to generate or modify a computational model. The method also includes running simulations using the computational model in accordance with the user input. After running the simulations, the method further includes determining results from the simulations. The results correspond to probable effects or outcomes of performing real life surgical operations or non-surgical invasive procedures corresponding to the user input. Last, the method includes presenting the results to the user via the user interface.

公开(公告)号：US08555317B2

公开(公告)日：2013-10-08

申请号：US13099914

申请日：2011-05-03

申请人： Wei Wei Ada Cho ,  Stephen R. Husak ,  Liang Ge ,  Aamer Hydrie

发明人： Wei Wei Ada Cho ,  Stephen R. Husak ,  Liang Ge ,  Aamer Hydrie

IPC分类号： G06F3/00 ,  G06F13/00 ,  H04N5/445

CPC分类号： H04N21/2665 ,  H04N7/17318 ,  H04N21/26283 ,  H04N21/26291 ,  H04N21/26603 ,  H04N21/462 ,  H04N21/4622 ,  H04N21/84

摘要： Aggregating media content catalog data from a plurality of content providers. The catalog data is merged according to rules and provided to a user on a scheduled basis or on demand. In an embodiment, the merged catalog data represents an incremental update to previously delivered catalog data.

公开(公告)号：US08453085B2

公开(公告)日：2013-05-28

申请号：US13031953

申请日：2011-02-22

申请人： Liang Ge ,  Gong Qiong Li ,  Suo Ming Pu ,  Chen Xu

发明人： Liang Ge ,  Gong Qiong Li ,  Suo Ming Pu ,  Chen Xu

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/62 ,  G06F2217/84

摘要： Estimating the latency time of the clock tree of an ASIC including: providing a netlist and a placement related to the clock tree of the ASIC; extracting a number of the load timing devices connected by the clock tree according to the netlist related to the clock tree; extracting a physical distribution area of the load timing devices connected by the clock tree according to the placement related to the clock tree; estimating a latency time of the clock tree according to the relationship between the number of the load timing devices, the physical distribution area of the load timing devices and latency time of the clock tree in design data related to the ASIC design.

摘要翻译： 估计ASIC的时钟树的延迟时间，包括：提供与ASIC的时钟树相关的网表和布局; 根据与时钟树相关联的网表提取由时钟树连接的多个负载定时设备; 根据与时钟树相关的位置提取由时钟树连接的负载定时设备的物理分配区域; 根据负载定时装置的数量，负载定时装置的物理分配面积和与ASIC设计有关的设计数据中的时钟树的延迟时间之间的关系来估计时钟树的等待时间。

公开(公告)号：US20120110541A1

公开(公告)日：2012-05-03

申请号：US13280146

申请日：2011-10-24

申请人： Liang Ge ,  Xia Li ,  Jia Lian Tang ,  Xiao Feng Tang ,  Chen Xu

发明人： Liang Ge ,  Xia Li ,  Jia Lian Tang ,  Xiao Feng Tang ,  Chen Xu

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5031 ,  G06F2217/84

摘要： Functionality can be implemented for optimizing connection constraints in an integrated circuit design. A target timing path associated with a first of a plurality of sub-connections of the integrated circuit is determined. A timing probability value and a route probability value associated with the first of the plurality of sub-connections is determined based, at least in part, on the target timing path associated with the first of the plurality of sub-connections. The timing probability value indicates a probability that timing closure is satisfied on the target timing path. The route probability value indicates a probability that a physical routing track on the target timing path associated with the first of the plurality of sub-connections resolves congestion. A current connection constraint associated with the first of the plurality of sub-connections is modified in accordance with a connection constraint model to which the first of the plurality of sub-connections corresponds.

摘要翻译： 可以实现功能，以优化集成电路设计中的连接约束。 确定与集成电路的多个子连接中的第一个相关联的目标定时路径。 至少部分地基于与多个子连接中的第一个相关联的目标定时路径来确定与多个子连接中的第一个子连接相关联的定时概率值和路线概率值。 定时概率值表示在目标定时路径上满足定时闭合的概率。 路由概率值指示与多个子连接中的第一个相关联的目标定时路径上的物理路由轨迹解决拥塞的概率。 与多个子连接中的第一个连接相关联的当前连接约束根据多个子连接中的第一个子连接对应的连接约束模型进行修改。

公开(公告)号：US20120047478A1

公开(公告)日：2012-02-23

申请号：US13031953

申请日：2011-02-22

申请人： Liang Ge ,  Gong Qiong Li ,  Suo Ming Pu ,  Chen Xu

发明人： Liang Ge ,  Gong Qiong Li ,  Suo Ming Pu ,  Chen Xu

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/62 ,  G06F2217/84

摘要： Estimating the latency time of the clock tree of an ASIC including: providing a netlist and a placement related to the clock tree of the ASIC; extracting a number of the load timing devices connected by the clock tree according to the netlist related to the clock tree; extracting a physical distribution area of the load timing devices connected by the clock tree according to the placement related to the clock tree; estimating a latency time of the clock tree according to the relationship between the number of the load timing devices, the physical distribution area of the load timing devices and latency time of the clock tree in design data related to the ASIC design.

摘要翻译： 估计ASIC的时钟树的延迟时间，包括：提供与ASIC的时钟树相关的网表和布局; 根据与时钟树相关联的网表提取由时钟树连接的多个负载定时设备; 根据与时钟树相关的位置提取由时钟树连接的负载定时设备的物理分配区域; 根据负载定时装置的数量，负载定时装置的物理分配面积和与ASIC设计有关的设计数据中的时钟树的延迟时间之间的关系来估计时钟树的等待时间。

公开(公告)号：US07984204B2

公开(公告)日：2011-07-19

申请号：US12119924

申请日：2008-05-13

申请人： Adrian S. Butter ,  Liang Chen ,  Liang Ge

发明人： Adrian S. Butter ,  Liang Chen ,  Liang Ge

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A Direct Memory Access controller controls access to memory in a data processing system via a system bus. The controller is made up of a data load unit configured for performing load operations with data. A data computation unit is configured for performing data conversion and is pipeline connected in sequence to the data load unit. A data store unit is also pipeline connected in sequence to the data computation unit and is configured for performing burst store operations onto a system bus for storage in system memory.

摘要翻译： 直接存储器访问控制器通过系统总线控制对数据处理系统中的存储器的访问。 控制器由配置为用数据执行加载操作的数据加载单元组成。 数据计算单元被配置为执行数据转换，并且被顺序连接到数据加载单元。 数据存储单元也被顺序地连接到数据计算单元，并且被配置为在系统总线上执行突发存储操作以存储在系统存储器中。

公开(公告)号：US20160371947A1

公开(公告)日：2016-12-22

申请号：US15254898

申请日：2016-09-01

申请人： Luke Isaac Neese ,  Liang Ge

发明人： Luke Isaac Neese ,  Liang Ge

IPC分类号： G08B13/16 ,  G08B21/18

CPC分类号： G08B13/1672 ,  G01H3/00 ,  G01S3/801 ,  G01S3/803 ,  G01S3/8032 ,  G01S7/539 ,  G08B21/182 ,  G08B25/08

摘要： A system for noise detection. Aspects of the system include a detection unit for detecting and responding to a predetermined noise such as a gunshot. In some embodiments, at least a portion of the unit may be utilized both within a confined space, such as a room in a building, or inside a machine, and in large environments such as outdoors. The detection unit may comprise a digital computing device, a digital-to-analog converter, a speaker acoustic output, a microphone acoustic input, an analog-to-digital converter, and a transmitter.

摘要翻译： 一种噪声检测系统。 系统的方面包括用于检测和响应诸如枪声的预定噪声的检测单元。 在一些实施例中，单元的至少一部分可以在密闭空间内，例如建筑物中的房间，或机器内部以及在诸如室外的大环境中使用。 检测单元可以包括数字计算设备，数模转换器，扬声器声输出，麦克风声输入，模数转换器和发射器。

公开(公告)号：US20130140625A1

公开(公告)日：2013-06-06

申请号：US13642286

申请日：2011-04-25

申请人： Yinghua Piao ,  Liang Ge ,  Dongping Wu ,  Shi-Li Zhang ,  Wei Zhang

发明人： Yinghua Piao ,  Liang Ge ,  Dongping Wu ,  Shi-Li Zhang ,  Wei Zhang

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66643 ,  H01L29/66659 ,  H01L29/7839

摘要： The present invention belongs to the field of microelectronic device technologies. Specifically, an asymmetric source/drain field-effect transistor and its methods of making are disclosed. A structure of the field-effect transistor comprises: a semiconductor substrate, a gate structure, and a source region and a drain region having a mixed junction and a P-N junction, respectively. The source region and the drain region are asymmetrical structured with respect to each other, one of which comprises a P-N junction, and the other of which comprises a mixed junction, the mixed junction being a combination of a Schottky junction and a P-N junction. According to the present disclosure, a location of a doped region formed by ion implantation is controlled by adjusting an implantation angle, and a unique structure is formed for the asymmetric source/drain field-effect transistor.

摘要翻译： 本发明属于微电子器件技术领域。 具体地说，公开了非对称源极/漏极场效应晶体管及其制造方法。 场效应晶体管的结构包括：半导体衬底，栅极结构，以及分别具有混合结和P-N结的源极区和漏极区。 源极区和漏极区彼此不对称地构成，其中之一包括P-N结，另一个包括混合结，该混合结是肖特基结和P-N结的组合。 根据本公开，通过调整注入角度来控制通过离子注入形成的掺杂区域的位置，并且为非对称源极/漏极场效应晶体管形成独特的结构。

公开(公告)号：US20120179407A1

公开(公告)日：2012-07-12

申请号：US13348527

申请日：2012-01-11

申请人： Liang GE ,  Xiaofan CHEN

发明人： Liang GE ,  Xiaofan CHEN

IPC分类号： G06F19/00 ,  G01K15/00

CPC分类号： G01K1/20 ,  G01K7/02 ,  G01K7/12

摘要： An I/O circuit for measuring temperatures uses multiple cold-junction compensation sensors permanently affixed near the terminals of the terminal block in order to compensate significant temperature variation across the terminals of the I/O module (up to 3° C.) that can substantially affect the accuracy of thermocouple measurements. The use of these multiple sensors is enabled by a compensation system that corrects for the distance between the built-in sensors and the terminals, a multiplexer that accommodates the additional signal burden produced by the sensors, and a compensation system that allows low-cost sensors to be used and calibrated to as little as a single high accuracy sensor. In one embodiment, a third temperature sensor with relatively higher accuracy is used to compensate for lower accuracy of permanently affixed sensors.

摘要翻译： 用于测量温度的I / O电路使用多个冷端补偿传感器，永久性地固定在接线端子端子附近，以补偿I / O模块端子（高达3°C）之间的显着温度变化， 基本上影响热电偶测量的精度。 这些多个传感器的使用通过补偿系统来实现，该补偿系统校正了内置传感器和终端之间的距离，一个适应传感器产生的附加信号负担的多路复用器，以及允许低成本传感器 被使用和校准到一个单一的高精度传感器。 在一个实施例中，使用具有相对较高精度的第三温度传感器来补偿永久固定的传感器的较低精度。

公开(公告)号：US20090287860A1

公开(公告)日：2009-11-19

申请号：US12119924

申请日：2008-05-13

申请人： Adrian S. Butter ,  Liang Chen ,  Liang Ge

发明人： Adrian S. Butter ,  Liang Chen ,  Liang Ge

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A Direct Memory Access controller controls access to memory in a data processing system via a system bus. The controller is made up of a data load unit configured for performing load operations with data. A data computation unit is configured for performing data conversion and is pipeline connected in sequence to the data load unit. A data store unit is also pipeline connected in sequence to the data computation unit and is configured for performing burst store operations onto a system bus for storage in system memory.

摘要翻译： 直接存储器访问控制器通过系统总线控制对数据处理系统中的存储器的访问。 控制器由配置为用数据执行加载操作的数据加载单元组成。 数据计算单元被配置为执行数据转换，并且被顺序连接到数据加载单元。 数据存储单元也被顺序地连接到数据计算单元，并且被配置为在系统总线上执行突发存储操作以存储在系统存储器中。