发明申请
US20120074559A1 INTEGRATED CIRCUIT PACKAGE USING THROUGH SUBSTRATE VIAS TO GROUND LID 审中-公开
使用通过基板VIAS的接地电路的集成电路封装

INTEGRATED CIRCUIT PACKAGE USING THROUGH SUBSTRATE VIAS TO GROUND LID
摘要:
An integrated circuit package including a package substrate, a metal lid mounted to the package substrate, and a stack of two or more integrated circuit chips electrically connected to each other by through substrate vias. The stack of two or more integrated circuit chips is disposed within the metal lid and electrically mounted to the package substrate. An inner surface of a top of the metal lid is electrically connected to ground wires in the package substrate by the through substrate vias. The TSVs provide electromagnetic interference shielding. A conductive thermal interface material may also be used. An alternative embodiment includes a single integrated circuit chip using TSVs to ground the metal lid.
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