公开(公告)号：US20120074559A1

公开(公告)日：2012-03-29

申请号：US12889586

申请日：2010-09-24

申请人： Timothy W. Budell ,  Mark C.H. Lamorey ,  Peter Slota, JR.

发明人： Timothy W. Budell ,  Mark C.H. Lamorey ,  Peter Slota, JR.

IPC分类号： H01L23/29

CPC分类号： H01L23/055 ,  H01L23/42 ,  H01L23/481 ,  H01L23/552 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

摘要： An integrated circuit package including a package substrate, a metal lid mounted to the package substrate, and a stack of two or more integrated circuit chips electrically connected to each other by through substrate vias. The stack of two or more integrated circuit chips is disposed within the metal lid and electrically mounted to the package substrate. An inner surface of a top of the metal lid is electrically connected to ground wires in the package substrate by the through substrate vias. The TSVs provide electromagnetic interference shielding. A conductive thermal interface material may also be used. An alternative embodiment includes a single integrated circuit chip using TSVs to ground the metal lid.

摘要翻译： 一种集成电路封装，其包括封装基板，安装到封装基板的金属盖，以及通过基板通孔彼此电连接的两个或多个集成电路芯片的堆叠。 两个或多个集成电路芯片的堆叠被布置在金属盖内并电安装到封装基板。 金属盖的顶部的内表面通过贯穿基板通孔与封装衬底中的接地线电连接。 TSV提供电磁干扰屏蔽。 还可以使用导电热界面材料。 一个替代实施例包括使用TSV来对金属盖进行接地的单个集成电路芯片。

公开(公告)号：US20120187953A1

公开(公告)日：2012-07-26

申请号：US13010057

申请日：2011-01-20

申请人： Luke D. LACROIX ,  Mark C.H. Lamorey ,  Steven F. Oakland ,  Janak G. Patel ,  Kerry P. Pfarr ,  Peter Slota, JR. ,  David B. Stone

发明人： Luke D. LACROIX ,  Mark C.H. Lamorey ,  Steven F. Oakland ,  Janak G. Patel ,  Kerry P. Pfarr ,  Peter Slota, JR. ,  David B. Stone

IPC分类号： G01R31/02

CPC分类号： G01R31/2884 ,  G01R31/2896 ,  H01L21/76895 ,  H01L22/32

摘要： Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.

摘要翻译： 本文提供了检测电路，使用和制造方法以及设计结构。 该结构包括穿过集成电路的一个或多个金属层的至少一个信号线。 电路耦合到所述至少一个信号线，其被构造为接收具有来自至少一个信号线的已知信号或来自不同电位的信号的信号，并且基于哪个信号被接收，确定是否存在 集成电路中的结构缺陷。

公开(公告)号：US20130292817A1

公开(公告)日：2013-11-07

申请号：US13461912

申请日：2012-05-02

申请人： Luke D. LaCroix ,  Mark Lamorey ,  Janak G. Patel ,  Peter Slota, JR. ,  David B. Stone

发明人： Luke D. LaCroix ,  Mark Lamorey ,  Janak G. Patel ,  Peter Slota, JR. ,  David B. Stone

IPC分类号： H01L23/48 ,  H01L21/66

CPC分类号： H01L22/34 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5283 ,  H01L23/5329 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/0554 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/14515 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/05552

摘要： A structure and method for monitoring interlevel dielectric stress damage. The structure includes a monitor solder bump and normal solder bumps; a set of stacked interlevel dielectric layers between the substrate and the monitor solder bump and the normal solder bumps, one or more ultra-low K dielectric layers comprising an ultra-low K material having a dielectric constant of 2.4 or less; a monitor structure in a region directly under the monitor solder bump in the ultra-low K dielectric layers and wherein the conductor density in at least one ultra-low K dielectric layer in the region directly under the monitor solder bumps is less than a specified minimum density and the conductor density in corresponding regions of the ultra-low K dielectric layers directly under normal solder bumps is greater than the specified minimum density.

摘要翻译： 一种用于监测层间介电应力损伤的结构和方法。 该结构包括一个监测焊锡凸块和一般焊锡凸块; 在衬底和监测焊料凸点之间的一组层叠的层间电介质层和正常的焊料凸点，一个或多个包含介电常数为2.4或更小的超低K材料的超低K电介质层; 在超低K电介质层中的监视器焊料凸块正下方的区域中的监视器结构，并且其中在监视器焊料凸块正下方的区域中的至少一个超低K电介质层中的导体密度小于规定的最小值 正常焊锡凸块下的超低K电介质层的相应区域的密度和导体密度大于规定的最小密度。

公开(公告)号：US20130285251A1

公开(公告)日：2013-10-31

申请号：US13459785

申请日：2012-04-30

申请人： Luke D. LaCroix ,  Mark C. H. Lamorey ,  Janak G. Patel ,  Peter Slota, JR. ,  David B. Stone

发明人： Luke D. LaCroix ,  Mark C. H. Lamorey ,  Janak G. Patel ,  Peter Slota, JR. ,  David B. Stone

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L21/768 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure comprises a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.

摘要翻译： 集成电路结构包括形成层叠结构的多个绝缘体层（彼此连接）。 进一步包括在每个绝缘体层内的开口，以及通孔开口内的导电通孔材料。 相邻绝缘体层的对应的通孔内的导电通孔材料电连接以形成通过层压结构的顶表面和底表面之间的绝缘体层的连续的电通路。 在每个连续的电通路中，通孔相对于彼此定位，以形成通过层压结构的导电过孔材料的对角线结构路径。 相邻绝缘体层的相应通孔开始部分重叠。 对角结构路径与顶面和底面非垂直。

公开(公告)号：US20120049874A1

公开(公告)日：2012-03-01

申请号：US12862844

申请日：2010-08-25

申请人： Luke D. LaCroix ,  Janak G. Patel ,  Peter Slota, JR. ,  David B. Stone

发明人： Luke D. LaCroix ,  Janak G. Patel ,  Peter Slota, JR. ,  David B. Stone

IPC分类号： G01R31/26

CPC分类号： G01R31/2856 ,  G01R31/2875

摘要： A semiconductor test device including a plurality of conductive layers, each of the layers comprising integrated circuit devices, a plurality of insulating layers between the conductive layers, a plurality of heat generating structures positioned between the insulating layers and the conductive layers, each of the heat generating structures being sized and positioned to only heat a predetermined limited area of the plurality of layers, a plurality of thermal monitors positioned within each of the plurality of layers, a control unit operatively connected to the heat generating structures and the thermal monitors, the control unit individually cycling the heat generating structures on and off for multiple heat cycles, such that different areas of the layers are treated to different heat cycles.

摘要翻译： 一种半导体测试装置，包括多个导电层，每个层包括集成电路器件，导电层之间的多个绝缘层，位于绝缘层和导电层之间的多个发热结构，每个热量 产生的结构的大小和位置仅仅加热多个层中的预定限制区域，多个位于多个层中的每一个层内的热监测器，可操作地连接到发热结构和热监测器的控制单元， 单元单独地将发热结构打开和关闭多个热循环，使得不同的层的区域被处理到不同的热循环。