Invention Application
US20120098621A1 PATTERNED CAPACITOR GROUND SHIELD FOR INDUCTOR IN AN INTEGRATED CIRCUIT
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集成电路中电感器的图形电容器接地屏蔽
- Patent Title: PATTERNED CAPACITOR GROUND SHIELD FOR INDUCTOR IN AN INTEGRATED CIRCUIT
- Patent Title (中): 集成电路中电感器的图形电容器接地屏蔽
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Application No.: US13340622Application Date: 2011-12-29
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Publication No.: US20120098621A1Publication Date: 2012-04-26
- Inventor: Lalitkumar Nathawad
- Applicant: Lalitkumar Nathawad
- Applicant Address: US CA San Jose
- Assignee: Qualcomm Atheros, Inc.
- Current Assignee: Qualcomm Atheros, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H03H7/01
- IPC: H03H7/01 ; H01L21/02
Abstract:
Integrated circuits are disclosed including at least one inductor-capacitor component, where each of the inductor-capacitor components includes an inductor and a capacitor constructed between the inductor and a substrate. The inductor includes at least one metal loop over a shield pattern forming a first capacitor terminal over patterned oxide layer with a second capacitor layer between the patterned oxide layer and the substrate.
Public/Granted literature
- US08187944B2 Patterned capacitor ground shield for inductor in an integrated circuit Public/Granted day:2012-05-29
Information query
