公开(公告)号：US07728631B2

公开(公告)日：2010-06-01

申请号：US12120827

申请日：2008-05-15

Applicant: Lalitkumar Nathawad

Inventor： Lalitkumar Nathawad

IPC: H03D13/00

CPC classification number: H03L7/1976 ,  H03L7/0891

Abstract: A phase frequency detector comprising a detection circuit and a reset circuit. The phase frequency detector may receive a feedback signal having a predetermined pulse width. The detection circuit may generate a first control signal based on a reference signal, and a second control signal based on the feedback signal. The reset circuit may generate a reset signal used for resetting the detection circuit based on the first control signal, the second control signal, and the feedback signal. The feedback signal may be tied to the generation of the reset signal such that, during a locked state, the pulse width of the second control signal is approximately equal to the pulse width of the feedback signal, which helps reduce the sensitivity of the circuit to nonlinearities.

Abstract translation: 一种相位频率检测器，包括检测电路和复位电路。 相位频率检测器可以接收具有预定脉冲宽度的反馈信号。 检测电路可以基于参考信号产生第一控制信号，并且基于反馈信号产生第二控制信号。 复位电路可以基于第一控制信号，第二控制信号和反馈信号产生用于复位检测电路的复位信号。 反馈信号可以与复位信号的产生相关联，使得在锁定状态期间，第二控制信号的脉冲宽度近似等于反馈信号的脉冲宽度，这有助于将电路的灵敏度降低到 非线性

公开(公告)号：US20120098621A1

公开(公告)日：2012-04-26

申请号：US13340622

申请日：2011-12-29

Applicant: Lalitkumar Nathawad

Inventor： Lalitkumar Nathawad

IPC: H03H7/01 ,  H01L21/02

CPC classification number: H01L28/10 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L27/0629 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits are disclosed including at least one inductor-capacitor component, where each of the inductor-capacitor components includes an inductor and a capacitor constructed between the inductor and a substrate. The inductor includes at least one metal loop over a shield pattern forming a first capacitor terminal over patterned oxide layer with a second capacitor layer between the patterned oxide layer and the substrate.

Abstract translation: 公开了集成电路，其包括至少一个电感器 - 电容器部件，其中每个电感器 - 电容器部件包括电感器和构造在电感器和基板之间的电容器。 电感器包括屏蔽图案上的至少一个金属环，其在图案化氧化物层上形成第一电容器端子，在图案化氧化物层和衬底之间具有第二电容器层。

公开(公告)号：US07728676B2

公开(公告)日：2010-06-01

申请号：US12112914

申请日：2008-04-30

Applicant: Lalitkumar Nathawad ,  Justin Hwang

Inventor： Lalitkumar Nathawad ,  Justin Hwang

IPC: H03L7/00

CPC classification number: H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1253 ,  H03B5/1265 ,  H03B2201/025 ,  H03J2200/10

Abstract: A voltage-controlled oscillator (VCO) comprising a first circuit, a second circuit, a comparator circuit, and a control unit. The first circuit can determine an output common mode voltage associated with an output of the VCO. The second circuit can generate an upper control voltage limit and a lower control voltage limit associated with a control voltage received by the VCO based, at least in part, on the output common mode voltage. The comparator circuit can compare the control voltage to the upper and lower control voltage limits. The control unit can determine whether to change a switched capacitance associated with the VCO based, at least in part, on whether the control voltage is outside the upper and lower control voltage limits, thereby maintaining an optimal region of operation for the control voltage.

Abstract translation: 一种包括第一电路，第二电路，比较器电路和控制单元的压控振荡器（VCO）。 第一电路可以确定与VCO的输出相关联的输出共模电压。 第二电路可以至少部分地基于输出共模电压产生与VCO接收的控制电压相关联的较高控制电压限制和较低控制电压限制。 比较器电路可以将控制电压与上下限电压限制进行比较。 至少部分地基于控制电压是否超出上限和下限控制电压限制，控制单元可以确定是否改变与VCO相关联的开关电容，从而保持控制电压的最佳操作区域。

公开(公告)号：US20090285279A1

公开(公告)日：2009-11-19

申请号：US12120827

申请日：2008-05-15

Applicant: Lalitkumar Nathawad

Inventor： Lalitkumar Nathawad

IPC: H03K7/08 ,  H03K9/08

CPC classification number: H03L7/1976 ,  H03L7/0891

Abstract: A phase frequency detector comprising a detection circuit and a reset circuit. The phase frequency detector may receive a feedback signal having a predetermined pulse width. The detection circuit may generate a first control signal based on a reference signal, and a second control signal based on the feedback signal. The reset circuit may generate a reset signal used for resetting the detection circuit based on the first control signal, the second control signal, and the feedback signal. The feedback signal may be tied to the generation of the reset signal such that, during a locked state, the pulse width of the second control signal is approximately equal to the pulse width of the feedback signal, which helps reduce the sensitivity of the circuit to nonlinearities.

Abstract translation: 一种相位频率检测器，包括检测电路和复位电路。 相位频率检测器可以接收具有预定脉冲宽度的反馈信号。 检测电路可以基于参考信号产生第一控制信号，并且基于反馈信号产生第二控制信号。 复位电路可以基于第一控制信号，第二控制信号和反馈信号产生用于复位检测电路的复位信号。 反馈信号可以与复位信号的产生相关联，使得在锁定状态期间，第二控制信号的脉冲宽度近似等于反馈信号的脉冲宽度，这有助于将电路的灵敏度降低到 非线性

公开(公告)号：US09122481B2

公开(公告)日：2015-09-01

申请号：US13540488

申请日：2012-07-02

Applicant: Manoj Unnikrishnan ,  Sarvesh Shrivastava ,  Lalitkumar Nathawad

Inventor： Manoj Unnikrishnan ,  Sarvesh Shrivastava ,  Lalitkumar Nathawad

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/3209 ,  G06F1/3278 ,  G06F13/4282 ,  Y02D10/157 ,  Y02D50/20

Abstract: In a serial communication system having a device including a receiver detection module, this specification is directed to systems and methods for selectively reducing the power consumed by the receiver detection module, preferably when the device is operating in a low power mode. In some embodiments, a signal detection module is configured to receive a control signal from the transmitter of a device at the other end of the communications link to control the operation of the receiver detection module. The control signal may be in-band or may be transmitted on a sideband of the serial link.

Abstract translation: 在具有包括接收机检测模块的设备的串行通信系统中，本说明书涉及用于选择性地降低接收机检测模块消耗的功率的系统和方法，优选地当设备以低功率模式工作时。 在一些实施例中，信号检测模块被配置为从通信链路的另一端处的设备的发射机接收控制信号，以控制接收机检测模块的操作。 控制信号可以是带内的或可以在串行链路的边带上传输。

公开(公告)号：US20090072910A1

公开(公告)日：2009-03-19

申请号：US12112914

申请日：2008-04-30

Applicant: Lalitkumar Nathawad ,  Justin Hwang

Inventor： Lalitkumar Nathawad ,  Justin Hwang

IPC: H03B5/18 ,  H03L7/06

CPC classification number: H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1253 ,  H03B5/1265 ,  H03B2201/025 ,  H03J2200/10

Abstract: A voltage-controlled oscillator (VCO) comprising a first circuit, a second circuit, a comparator circuit, and a control unit. The first circuit can determine an output common mode voltage associated with an output of the VCO. The second circuit can generate an upper control voltage limit and a lower control voltage limit associated with a control voltage received by the VCO based, at least in part, on the output common mode voltage. The comparator circuit can compare the control voltage to the upper and lower control voltage limits. The control unit can determine whether to change a switched capacitance associated with the VCO based, at least in part, on whether the control voltage is outside the upper and lower control voltage limits, thereby maintaining an optimal region of operation for the control voltage.

Abstract translation: 一种包括第一电路，第二电路，比较器电路和控制单元的压控振荡器（VCO）。 第一电路可以确定与VCO的输出相关联的输出共模电压。 第二电路可以至少部分地基于输出共模电压产生与VCO接收的控制电压相关联的较高控制电压限制和较低控制电压限制。 比较器电路可以将控制电压与上下限电压限制进行比较。 至少部分地基于控制电压是否超出上限和下限控制电压限制，控制单元可以确定是否改变与VCO相关联的开关电容，从而保持控制电压的最佳操作区域。

公开(公告)号：US07414555B1

公开(公告)日：2008-08-19

申请号：US11531677

申请日：2006-09-13

Applicant: Lalitkumar Nathawad ,  David J. Weber ,  Masoud Zargari

Inventor： Lalitkumar Nathawad ,  David J. Weber ,  Masoud Zargari

IPC: H03M1/00

CPC classification number: H03M1/1215

Abstract: An interleaved ADC can advantageously provide synchronous sampling and time-multiplexed output. Differential I and Q input signals can first be stored by charging a plurality of capacitors. These stored differential signals can be buffered in a time-multiplexed sequence. For example, buffering can include transferring voltages stored by a first set of capacitors at a first time and then transferring voltages stored by a second set of capacitors at a second time. Advantageously, this time-multiplexing allow the ADC to be significantly smaller than conventional implementations of two-input ADCs. A folded mixer with gain control is also provided. This mixer can include a first stage having a first set of inductors and a plurality of first type transistors and a second stage having a second set of inductors and a plurality of second type transistors. The plurality of second type transistors in the second stage, which are in a folded configuration, can be driven by the first set of inductors in the first stage. The outputs of the mixer are positioned between the plurality of second type transistors and the second set of inductors. This configuration advantageously permits the mixer to use a low operating voltage.

Abstract translation: 交错ADC可以有利地提供同步采样和时间复用输出。 可以通过对多个电容器充电来首先存储差分I和Q输入信号。 这些存储的差分信号可以以时间复用顺序被缓冲。 例如，缓冲可以包括在第一时间转移由第一组电容器存储的电压，然后在第二时间传送由第二组电容器存储的电压。 有利地，该时间复用允许ADC比双输入ADC的传统实现方式显着更小。 还提供了具有增益控制的折叠混合器。 该混频器可以包括具有第一组电感器和多个第一类型晶体管的第一级和具有第二组电感器和多个第二类型晶体管的第二级。 处于折叠构造的第二级中的多个第二类型晶体管可以由第一级中的第一组电感器驱动。 混频器的输出位于多个第二类型晶体管和第二组电感器之间。 该配置有利地允许混合器使用低工作电压。

公开(公告)号：US08187944B2

公开(公告)日：2012-05-29

申请号：US13340622

申请日：2011-12-29

Applicant: Lalitkumar Nathawad

Inventor： Lalitkumar Nathawad

IPC: H01L27/00 ,  H01L21/20

CPC classification number: H01L28/10 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L27/0629 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits are disclosed including at least one inductor-capacitor component, where each of the inductor-capacitor components includes an inductor and a capacitor constructed between the inductor and a substrate. The inductor includes at least one metal loop over a shield pattern forming a first capacitor terminal over patterned oxide layer with a second capacitor layer between the patterned oxide layer and the substrate.

Abstract translation: 公开了集成电路，其包括至少一个电感器 - 电容器部件，其中每个电感器 - 电容器部件包括电感器和构造在电感器和基板之间的电容器。 电感器包括屏蔽图案上的至少一个金属环，其在图案化氧化物层上形成第一电容器端子，在图案化氧化物层和衬底之间具有第二电容器层。

公开(公告)号：US08107913B1

公开(公告)日：2012-01-31

申请号：US12437442

申请日：2009-05-07

Applicant: Lalitkumar Nathawad

Inventor： Lalitkumar Nathawad

IPC: H04B1/06

CPC classification number: H03G3/3052 ,  H03B2200/0034

Abstract: A digital regulated Local Oscillator (LO) buffer receives an unregulated LO signal from a local oscillator to create a regulated LO signal. Embodiments include not only the digital regulated LO buffer, but also a transceiver and/or a receiver including at least one instance of the digital LO buffer. They may be implemented as an integrated circuit. The digital regulated LO Buffer may include: A LO buffer receiving the unregulated LO signal and an amplitude control signal to create the regulated LO signal. A peak detector receives the regulated LO signal to create an analog peak signal that is presented to a digital output comparator along with a reference amplitude signal to create a digital threshold detect signal. An amplitude controller receives the digital threshold detect signal to create a digital control signal that drives a digitally controlled source to create the amplitude control signal.

Abstract translation: 数字调节本地振荡器（LO）缓冲器从本地振荡器接收未调节的LO信号以产生调节的LO信号。 实施例不仅包括数字调节的LO缓冲器，还包括收发器和/或包括数字LO缓冲器的至少一个实例的接收器。 它们可以被实现为集成电路。 数字调节LO缓冲器可以包括：LO缓冲器接收未调节的LO信号和振幅控制信号以产生调节的LO信号。 峰值检测器接收经调节的LO信号以产生模拟峰值信号，该模拟峰值信号与参考幅度信号一起提供给数字输出比较器以产生数字阈值检测信号。 幅度控制器接收数字阈值检测信号，以产生驱动数字控制源的数字控制信号以产生幅度控制信号。

公开(公告)号：US20130007489A1

公开(公告)日：2013-01-03

申请号：US13540488

申请日：2012-07-02

Applicant: Manoj Unnikrishnan ,  Sarvesh Shrivastava ,  Lalitkumar Nathawad

Inventor： Manoj Unnikrishnan ,  Sarvesh Shrivastava ,  Lalitkumar Nathawad

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/3209 ,  G06F1/3278 ,  G06F13/4282 ,  Y02D10/157 ,  Y02D50/20

Abstract: In a serial communication system having a device including a receiver detection module, this specification is directed to systems and methods for selectively reducing the power consumed by the receiver detection module, preferably when the device is operating in a low power mode. In some embodiments, a signal detection module is configured to receive a control signal from the transmitter of a device at the other end of the communications link to control the operation of the receiver detection module. The control signal may be in-band or may be transmitted on a sideband of the serial link.