A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set at a resistance value. While a selected bit line is set at a certain potential, word lines coupled to different memory cells, which are coupled in common to the selected bit line, are sequentially driven, so that different memory cells are accessed in a time-divisional mode.