Provided is a thin film transistor array panel that includes: a substrate; a gate line and a data line formed on the substrate and at least partially defining a pixel area; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor and formed in the pixel area; a first common electrode formed under the pixel electrode; a second common electrode formed on the pixel electrode. The pixel area includes an upper pixel area and a lower pixel area, the first common electrode is formed in the upper pixel area, and the second common electrode is formed in the lower pixel area. The pixel electrode includes an upper pixel electrode formed in the upper pixel area and a lower pixel electrode formed in the lower pixel area.